shujucaiji.sim.rpt

来自「通过ADC0809对模拟信号进行采样」· RPT 代码 · 共 275 行 · 第 1/3 页

The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                           ;
+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                         ; Output Port Name                                                                                            ; Output Port Type ;
+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; |shujucaiji|cnt10b:inst1|cqi[7]                                                                   ; |shujucaiji|cnt10b:inst1|cqi[7]~68                                                                          ; cout0            ;
; |shujucaiji|cnt10b:inst1|cqi[6]                                                                   ; |shujucaiji|cnt10b:inst1|cqi[6]~72                                                                          ; cout0            ;
; |shujucaiji|cnt10b:inst1|cqi[5]                                                                   ; |shujucaiji|cnt10b:inst1|cqi[5]~76                                                                          ; cout0            ;
; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[6] ; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella6~COUT ; cout0            ;
; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[5] ; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella5~COUT ; cout0            ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]               ; portadataout0    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[6]               ; portadataout1    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[5]               ; portadataout2    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[4]               ; portadataout3    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[2]               ; portadataout5    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[1]               ; portadataout6    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[0]               ; portadataout7    ;
; |shujucaiji|adcint:inst|regl[1]                                                                   ; |shujucaiji|adcint:inst|regl[1]                                                                             ; regout           ;
; |shujucaiji|adcint:inst|regl[0]                                                                   ; |shujucaiji|adcint:inst|regl[0]                                                                             ; regout           ;
; |shujucaiji|wren                                                                                  ; |shujucaiji|wren                                                                                            ; combout          ;
; |shujucaiji|adda                                                                                  ; |shujucaiji|adda                                                                                            ; padio            ;
; |shujucaiji|q[7]                                                                                  ; |shujucaiji|q[7]                                                                                            ; padio            ;
; |shujucaiji|q[6]                                                                                  ; |shujucaiji|q[6]                                                                                            ; padio            ;
; |shujucaiji|q[5]                                                                                  ; |shujucaiji|q[5]                                                                                            ; padio            ;
; |shujucaiji|q[4]                                                                                  ; |shujucaiji|q[4]                                                                                            ; padio            ;
; |shujucaiji|q[2]                                                                                  ; |shujucaiji|q[2]                                                                                            ; padio            ;
; |shujucaiji|q[1]                                                                                  ; |shujucaiji|q[1]                                                                                            ; padio            ;
; |shujucaiji|q[0]                                                                                  ; |shujucaiji|q[0]                                                                                            ; padio            ;
+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                                                                           ;
+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                         ; Output Port Name                                                                                            ; Output Port Type ;
+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; |shujucaiji|cnt10b:inst1|cqi[7]                                                                   ; |shujucaiji|cnt10b:inst1|cqi[7]~68                                                                          ; cout0            ;
; |shujucaiji|cnt10b:inst1|cqi[6]                                                                   ; |shujucaiji|cnt10b:inst1|cqi[6]~72                                                                          ; cout0            ;
; |shujucaiji|cnt10b:inst1|cqi[5]                                                                   ; |shujucaiji|cnt10b:inst1|cqi[5]~76                                                                          ; cout0            ;
; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[6] ; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella6~COUT ; cout0            ;
; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[5] ; |shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella5~COUT ; cout0            ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]               ; portadataout0    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[6]               ; portadataout1    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[5]               ; portadataout2    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[4]               ; portadataout3    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[2]               ; portadataout5    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[1]               ; portadataout6    ;
; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]     ; |shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[0]               ; portadataout7    ;
; |shujucaiji|adcint:inst|regl[1]                                                                   ; |shujucaiji|adcint:inst|regl[1]                                                                             ; regout           ;
; |shujucaiji|adcint:inst|regl[0]                                                                   ; |shujucaiji|adcint:inst|regl[0]                                                                             ; regout           ;
; |shujucaiji|adda                                                                                  ; |shujucaiji|adda                                                                                            ; padio            ;
; |shujucaiji|q[7]                                                                                  ; |shujucaiji|q[7]                                                                                            ; padio            ;
; |shujucaiji|q[6]                                                                                  ; |shujucaiji|q[6]                                                                                            ; padio            ;
; |shujucaiji|q[5]                                                                                  ; |shujucaiji|q[5]                                                                                            ; padio            ;
; |shujucaiji|q[4]                                                                                  ; |shujucaiji|q[4]                                                                                            ; padio            ;
; |shujucaiji|q[2]                                                                                  ; |shujucaiji|q[2]                                                                                            ; padio            ;
; |shujucaiji|q[1]                                                                                  ; |shujucaiji|q[1]                                                                                            ; padio            ;
; |shujucaiji|q[0]                                                                                  ; |shujucaiji|q[0]                                                                                            ; padio            ;
+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Wed May 07 13:13:37 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off shujucaiji -c shujucaiji
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      75.53 %
Info: Number of transitions in simulation is 36414
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed May 07 13:13:38 2008
    Info: Elapsed time: 00:00:01