coswave.tan.rpt

来自「主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8」· RPT 代码 · 共 335 行 · 第 1/4 页

; N/A           ; None        ; -5.643 ns ; clk_en ; lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[5] ; clock    ;
; N/A           ; None        ; -5.643 ns ; clk_en ; lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[6] ; clock    ;
; N/A           ; None        ; -5.643 ns ; clk_en ; lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[7] ; clock    ;
+---------------+-------------+-----------+--------+---------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Wed Jan 01 00:59:20 2003
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off coswave -c coswave --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 275.03 MHz between source register "lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[1]" and destination register "lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[7]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.266 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y13_N1; Fanout = 4; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[1]'
            Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X12_Y13_N1; Fanout = 2; COMB Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella1~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X12_Y13_N2; Fanout = 2; COMB Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella2~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X12_Y13_N3; Fanout = 2; COMB Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella3~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X12_Y13_N4; Fanout = 3; COMB Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella4~COUT'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X12_Y13_N7; Fanout = 2; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[7]'
            Info: Total cell delay = 1.737 ns ( 76.65 % )
            Info: Total interconnect delay = 0.529 ns ( 23.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.767 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'clock'
                Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X12_Y13_N7; Fanout = 2; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[7]'
                Info: Total cell delay = 2.180 ns ( 78.79 % )
                Info: Total interconnect delay = 0.587 ns ( 21.21 % )
            Info: - Longest clock path from clock "clock" to source register is 2.767 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'clock'
                Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X12_Y13_N1; Fanout = 4; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[1]'
                Info: Total cell delay = 2.180 ns ( 78.79 % )
                Info: Total interconnect delay = 0.587 ns ( 21.21 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]" (data pin = "clk_en", clock pin = "clock") is 5.695 ns
    Info: + Longest pin to register delay is 8.425 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_107; Fanout = 8; PIN Node = 'clk_en'
        Info: 2: + IC(6.089 ns) + CELL(0.867 ns) = 8.425 ns; Loc. = LC_X12_Y13_N0; Fanout = 4; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]'
        Info: Total cell delay = 2.336 ns ( 27.73 % )
        Info: Total interconnect delay = 6.089 ns ( 72.27 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'clock'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X12_Y13_N0; Fanout = 4; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: tco from clock "clock" to destination pin "q[1]" through memory "data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|ram_block1a9~porta_address_reg0" is 13.019 ns
    Info: + Longest clock path from clock "clock" to source memory is 2.792 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'clock'
        Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y13; Fanout = 10; MEM Node = 'data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|ram_block1a9~porta_address_reg0'
        Info: Total cell delay = 2.191 ns ( 78.47 % )
        Info: Total interconnect delay = 0.601 ns ( 21.53 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Longest memory to pin delay is 9.577 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y13; Fanout = 10; MEM Node = 'data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|ram_block1a9~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y13; Fanout = 1; MEM Node = 'data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[1]'
        Info: 3: + IC(3.161 ns) + CELL(2.108 ns) = 9.577 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'q[1]'
        Info: Total cell delay = 6.416 ns ( 66.99 % )
        Info: Total interconnect delay = 3.161 ns ( 33.01 % )
Info: th for register "lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]" (data pin = "clk_en", clock pin = "clock") is -5.643 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'clock'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X12_Y13_N0; Fanout = 4; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.425 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_107; Fanout = 8; PIN Node = 'clk_en'
        Info: 2: + IC(6.089 ns) + CELL(0.867 ns) = 8.425 ns; Loc. = LC_X12_Y13_N0; Fanout = 4; REG Node = 'lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]'
        Info: Total cell delay = 2.336 ns ( 27.73 % )
        Info: Total interconnect delay = 6.089 ns ( 72.27 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jan 01 00:59:21 2003
    Info: Elapsed time: 00:00:02