coswave.map.eqn

主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；

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--E1_q_a[9] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[9]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[9]_PORT_A_address_reg = DFFE(E1_q_a[9]_PORT_A_address, E1_q_a[9]_clock_0, , , );
E1_q_a[9]_clock_0 = clock;
E1_q_a[9]_PORT_A_data_out = MEMORY(, , E1_q_a[9]_PORT_A_address_reg, , , , , , E1_q_a[9]_clock_0, , , , , );
E1_q_a[9] = E1_q_a[9]_PORT_A_data_out[0];


--E1_q_a[8] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[8]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[8]_PORT_A_address_reg = DFFE(E1_q_a[8]_PORT_A_address, E1_q_a[8]_clock_0, , , );
E1_q_a[8]_clock_0 = clock;
E1_q_a[8]_PORT_A_data_out = MEMORY(, , E1_q_a[8]_PORT_A_address_reg, , , , , , E1_q_a[8]_clock_0, , , , , );
E1_q_a[8] = E1_q_a[8]_PORT_A_data_out[0];


--E1_q_a[7] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[7]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = clock;
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out[0];


--E1_q_a[6] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[6]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_clock_0 = clock;
E1_q_a[6]_PORT_A_data_out = MEMORY(, , E1_q_a[6]_PORT_A_address_reg, , , , , , E1_q_a[6]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out[0];


--E1_q_a[5] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[5]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_clock_0 = clock;
E1_q_a[5]_PORT_A_data_out = MEMORY(, , E1_q_a[5]_PORT_A_address_reg, , , , , , E1_q_a[5]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out[0];


--E1_q_a[4] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = clock;
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];


--E1_q_a[3] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[3]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_clock_0 = clock;
E1_q_a[3]_PORT_A_data_out = MEMORY(, , E1_q_a[3]_PORT_A_address_reg, , , , , , E1_q_a[3]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out[0];


--E1_q_a[2] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = clock;
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];


--E1_q_a[1] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = clock;
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];


--E1_q_a[0] is data_rom:inst|altsyncram:altsyncram_component|altsyncram_6bu:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(G1_safe_q[0], G1_safe_q[1], G1_safe_q[2], G1_safe_q[3], G1_safe_q[4], G1_safe_q[5], G1_safe_q[6], G1_safe_q[7]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = clock;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--G1_safe_q[0] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[0]
--operation mode is arithmetic

G1_safe_q[0]_lut_out = !G1_safe_q[0];
G1_safe_q[0] = DFFEAS(G1_safe_q[0]_lut_out, clock, !reset, , clk_en, , , , );

--G1L2 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

G1L2 = CARRY(G1_safe_q[0]);


--G1_safe_q[1] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[1]
--operation mode is arithmetic

G1_safe_q[1]_carry_eqn = G1L2;
G1_safe_q[1]_lut_out = G1_safe_q[1] $ (G1_safe_q[1]_carry_eqn);
G1_safe_q[1] = DFFEAS(G1_safe_q[1]_lut_out, clock, !reset, , clk_en, , , , );

--G1L4 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

G1L4 = CARRY(!G1L2 # !G1_safe_q[1]);


--G1_safe_q[2] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[2]
--operation mode is arithmetic

G1_safe_q[2]_carry_eqn = G1L4;
G1_safe_q[2]_lut_out = G1_safe_q[2] $ (!G1_safe_q[2]_carry_eqn);
G1_safe_q[2] = DFFEAS(G1_safe_q[2]_lut_out, clock, !reset, , clk_en, , , , );

--G1L6 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

G1L6 = CARRY(G1_safe_q[2] & (!G1L4));


--G1_safe_q[3] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[3]
--operation mode is arithmetic

G1_safe_q[3]_carry_eqn = G1L6;
G1_safe_q[3]_lut_out = G1_safe_q[3] $ (G1_safe_q[3]_carry_eqn);
G1_safe_q[3] = DFFEAS(G1_safe_q[3]_lut_out, clock, !reset, , clk_en, , , , );

--G1L8 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

G1L8 = CARRY(!G1L6 # !G1_safe_q[3]);


--G1_safe_q[4] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[4]
--operation mode is arithmetic

G1_safe_q[4]_carry_eqn = G1L8;
G1_safe_q[4]_lut_out = G1_safe_q[4] $ (!G1_safe_q[4]_carry_eqn);
G1_safe_q[4] = DFFEAS(G1_safe_q[4]_lut_out, clock, !reset, , clk_en, , , , );

--G1L10 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

G1L10 = CARRY(G1_safe_q[4] & (!G1L8));


--G1_safe_q[5] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[5]
--operation mode is arithmetic

G1_safe_q[5]_carry_eqn = G1L10;
G1_safe_q[5]_lut_out = G1_safe_q[5] $ (G1_safe_q[5]_carry_eqn);
G1_safe_q[5] = DFFEAS(G1_safe_q[5]_lut_out, clock, !reset, , clk_en, , , , );

--G1L12 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

G1L12 = CARRY(!G1L10 # !G1_safe_q[5]);


--G1_safe_q[6] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[6]
--operation mode is arithmetic

G1_safe_q[6]_carry_eqn = G1L12;
G1_safe_q[6]_lut_out = G1_safe_q[6] $ (!G1_safe_q[6]_carry_eqn);
G1_safe_q[6] = DFFEAS(G1_safe_q[6]_lut_out, clock, !reset, , clk_en, , , , );

--G1L14 is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

G1L14 = CARRY(G1_safe_q[6] & (!G1L12));


--G1_safe_q[7] is lpm_conter8:inst1|lpm_counter:lpm_counter_component|cntr_9he:auto_generated|safe_q[7]
--operation mode is normal

G1_safe_q[7]_carry_eqn = G1L14;
G1_safe_q[7]_lut_out = G1_safe_q[7] $ (G1_safe_q[7]_carry_eqn);
G1_safe_q[7] = DFFEAS(G1_safe_q[7]_lut_out, clock, !reset, , clk_en, , , , );


--clock is clock
--operation mode is input

clock = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--clk_en is clk_en
--operation mode is input

clk_en = INPUT();


--q[9] is q[9]
--operation mode is output

q[9] = OUTPUT(E1_q_a[9]);


--q[8] is q[8]
--operation mode is output

q[8] = OUTPUT(E1_q_a[8]);


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(E1_q_a[7]);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(E1_q_a[6]);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(E1_q_a[5]);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(E1_q_a[4]);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(E1_q_a[3]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(E1_q_a[2]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(E1_q_a[1]);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(E1_q_a[0]);