📄 moter.hier_info
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|moter
pwmout1 <= timer:inst.out1
rst => timer:inst.rst
clk => timer:inst.clk
cs => timer:inst.cs
oe => timer:inst.oe
we => timer:inst.we
addr[0] => timer:inst.addr[0]
addr[1] => timer:inst.addr[1]
addr[2] => timer:inst.addr[2]
addr[3] => timer:inst.addr[3]
addr[4] => timer:inst.addr[4]
addr[5] => timer:inst.addr[5]
addr[6] => timer:inst.addr[6]
addr[7] => timer:inst.addr[7]
data[0] <= timer:inst.data[0]
data[1] <= timer:inst.data[1]
data[2] <= timer:inst.data[2]
data[3] <= timer:inst.data[3]
data[4] <= timer:inst.data[4]
data[5] <= timer:inst.data[5]
data[6] <= timer:inst.data[6]
data[7] <= timer:inst.data[7]
data[8] <= timer:inst.data[8]
data[9] <= timer:inst.data[9]
data[10] <= timer:inst.data[10]
data[11] <= timer:inst.data[11]
data[12] <= timer:inst.data[12]
data[13] <= timer:inst.data[13]
data[14] <= timer:inst.data[14]
data[15] <= timer:inst.data[15]
pwmout2 <= timer:inst.out2
pwmout3 <= timer:inst.out3
pwmout4 <= timer:inst.out4
|moter|timer:inst
rst => TCON[15].ACLR
rst => TCON[14].ACLR
rst => TCON[13].ACLR
rst => TCON[12].ACLR
rst => TCON[11].ACLR
rst => TCON[10].ACLR
rst => TCON[9].ACLR
rst => TCON[8].ACLR
rst => TCON[7].ACLR
rst => TCON[6].ACLR
rst => TCON[5].ACLR
rst => TCON[4].ACLR
rst => TCON[3].ACLR
rst => TCON[2].ACLR
rst => TCON[1].ACLR
rst => TCON[0].ACLR
rst => TCNTB1[15].ACLR
rst => TCNTB1[14].ACLR
rst => TCNTB1[13].ACLR
rst => TCNTB1[12].ACLR
rst => TCNTB1[11].ACLR
rst => TCNTB1[10].ACLR
rst => TCNTB1[9].ACLR
rst => TCNTB1[8].ACLR
rst => TCNTB1[7].ACLR
rst => TCNTB1[6].ACLR
rst => TCNTB1[5].ACLR
rst => TCNTB1[4].ACLR
rst => TCNTB1[3].ACLR
rst => TCNTB1[2].ACLR
rst => TCNTB1[1].ACLR
rst => TCNTB1[0].ACLR
rst => TCMPB1[15].ACLR
rst => TCMPB1[14].ACLR
rst => TCMPB1[13].ACLR
rst => TCMPB1[12].ACLR
rst => TCMPB1[11].ACLR
rst => TCMPB1[10].ACLR
rst => TCMPB1[9].ACLR
rst => TCMPB1[8].ACLR
rst => TCMPB1[7].ACLR
rst => TCMPB1[6].ACLR
rst => TCMPB1[5].ACLR
rst => TCMPB1[4].ACLR
rst => TCMPB1[3].ACLR
rst => TCMPB1[2].ACLR
rst => TCMPB1[1].ACLR
rst => TCMPB1[0].ACLR
rst => TCNT1[15].ACLR
rst => TCNT1[14].ACLR
rst => TCNT1[13].ACLR
rst => TCNT1[12].ACLR
rst => TCNT1[11].ACLR
rst => TCNT1[10].ACLR
rst => TCNT1[9].ACLR
rst => TCNT1[8].ACLR
rst => TCNT1[7].ACLR
rst => TCNT1[6].ACLR
rst => TCNT1[5].ACLR
rst => TCNT1[4].ACLR
rst => TCNT1[3].ACLR
rst => TCNT1[2].ACLR
rst => TCNT1[1].ACLR
rst => TCNT1[0].ACLR
rst => TCMP1[15].ACLR
rst => TCMP1[14].ACLR
rst => TCMP1[13].ACLR
rst => TCMP1[12].ACLR
rst => TCMP1[11].ACLR
rst => TCMP1[10].ACLR
rst => TCMP1[9].ACLR
rst => TCMP1[8].ACLR
rst => TCMP1[7].ACLR
rst => TCMP1[6].ACLR
rst => TCMP1[5].ACLR
rst => TCMP1[4].ACLR
rst => TCMP1[3].ACLR
rst => TCMP1[2].ACLR
rst => TCMP1[1].ACLR
rst => TCMP1[0].ACLR
rst => TDEADZONE[15].ACLR
rst => TDEADZONE[14].ACLR
rst => TDEADZONE[13].ACLR
rst => TDEADZONE[12].ACLR
rst => TDEADZONE[11].ACLR
rst => TDEADZONE[10].ACLR
rst => TDEADZONE[9].ACLR
rst => TDEADZONE[8].ACLR
rst => TDEADZONE[7].ACLR
rst => TDEADZONE[6].ACLR
rst => TDEADZONE[5].ACLR
rst => TDEADZONE[4].ACLR
rst => TDEADZONE[3].ACLR
rst => TDEADZONE[2].ACLR
rst => TDEADZONE[1].ACLR
rst => TDEADZONE[0].ACLR
rst => TCNTB2[15].ACLR
rst => TCNTB2[14].ACLR
rst => TCNTB2[13].ACLR
rst => TCNTB2[12].ACLR
rst => TCNTB2[11].ACLR
rst => TCNTB2[10].ACLR
rst => TCNTB2[9].ACLR
rst => TCNTB2[8].ACLR
rst => TCNTB2[7].ACLR
rst => TCNTB2[6].ACLR
rst => TCNTB2[5].ACLR
rst => TCNTB2[4].ACLR
rst => TCNTB2[3].ACLR
rst => TCNTB2[2].ACLR
rst => TCNTB2[1].ACLR
rst => TCNTB2[0].ACLR
rst => TCMPB2[15].ACLR
rst => TCMPB2[14].ACLR
rst => TCMPB2[13].ACLR
rst => TCMPB2[12].ACLR
rst => TCMPB2[11].ACLR
rst => TCMPB2[10].ACLR
rst => TCMPB2[9].ACLR
rst => TCMPB2[8].ACLR
rst => TCMPB2[7].ACLR
rst => TCMPB2[6].ACLR
rst => TCMPB2[5].ACLR
rst => TCMPB2[4].ACLR
rst => TCMPB2[3].ACLR
rst => TCMPB2[2].ACLR
rst => TCMPB2[1].ACLR
rst => TCMPB2[0].ACLR
rst => TCNT2[15].ACLR
rst => TCNT2[14].ACLR
rst => TCNT2[13].ACLR
rst => TCNT2[12].ACLR
rst => TCNT2[11].ACLR
rst => TCNT2[10].ACLR
rst => TCNT2[9].ACLR
rst => TCNT2[8].ACLR
rst => TCNT2[7].ACLR
rst => TCNT2[6].ACLR
rst => TCNT2[5].ACLR
rst => TCNT2[4].ACLR
rst => TCNT2[3].ACLR
rst => TCNT2[2].ACLR
rst => TCNT2[1].ACLR
rst => TCNT2[0].ACLR
rst => TCMP2[15].ACLR
rst => TCMP2[14].ACLR
rst => TCMP2[13].ACLR
rst => TCMP2[12].ACLR
rst => TCMP2[11].ACLR
rst => TCMP2[10].ACLR
rst => TCMP2[9].ACLR
rst => TCMP2[8].ACLR
rst => TCMP2[7].ACLR
rst => TCMP2[6].ACLR
rst => TCMP2[5].ACLR
rst => TCMP2[4].ACLR
rst => TCMP2[3].ACLR
rst => TCMP2[2].ACLR
rst => TCMP2[1].ACLR
rst => TCMP2[0].ACLR
rst => deadcount1[7].ACLR
rst => deadcount1[6].ACLR
rst => deadcount1[5].ACLR
rst => deadcount1[4].ACLR
rst => deadcount1[3].ACLR
rst => deadcount1[2].ACLR
rst => deadcount1[1].ACLR
rst => deadcount1[0].ACLR
rst => deadcount2[7].ACLR
rst => deadcount2[6].ACLR
rst => deadcount2[5].ACLR
rst => deadcount2[4].ACLR
rst => deadcount2[3].ACLR
rst => deadcount2[2].ACLR
rst => deadcount2[1].ACLR
rst => deadcount2[0].ACLR
rst => data[0]~en.ENA
rst => out4~reg0.ENA
rst => data[15]~reg0.ENA
rst => data[14]~reg0.ENA
rst => data[13]~reg0.ENA
rst => data[12]~reg0.ENA
rst => data[11]~reg0.ENA
rst => data[10]~reg0.ENA
rst => data[9]~reg0.ENA
rst => data[8]~reg0.ENA
rst => data[7]~reg0.ENA
rst => data[6]~reg0.ENA
rst => data[5]~reg0.ENA
rst => data[4]~reg0.ENA
rst => data[3]~reg0.ENA
rst => data[2]~reg0.ENA
rst => data[1]~reg0.ENA
rst => data[0]~reg0.ENA
rst => pwmout1.ENA
rst => deadpwmout1.ENA
rst => out1~reg0.ENA
rst => out2~reg0.ENA
rst => pwmout2.ENA
rst => deadpwmout2.ENA
rst => out3~reg0.ENA
rst => data[1]~en.ENA
rst => data[2]~en.ENA
rst => data[3]~en.ENA
rst => data[4]~en.ENA
rst => data[5]~en.ENA
rst => data[6]~en.ENA
rst => data[7]~en.ENA
rst => data[8]~en.ENA
rst => data[9]~en.ENA
rst => data[10]~en.ENA
rst => data[11]~en.ENA
rst => data[12]~en.ENA
rst => data[13]~en.ENA
rst => data[14]~en.ENA
rst => data[15]~en.ENA
clk => TCON[15].CLK
clk => TCON[14].CLK
clk => TCON[13].CLK
clk => TCON[12].CLK
clk => TCON[11].CLK
clk => TCON[10].CLK
clk => TCON[9].CLK
clk => TCON[8].CLK
clk => TCON[7].CLK
clk => TCON[6].CLK
clk => TCON[5].CLK
clk => TCON[4].CLK
clk => TCON[3].CLK
clk => TCON[2].CLK
clk => TCON[1].CLK
clk => TCON[0].CLK
clk => TCNTB1[15].CLK
clk => TCNTB1[14].CLK
clk => TCNTB1[13].CLK
clk => TCNTB1[12].CLK
clk => TCNTB1[11].CLK
clk => TCNTB1[10].CLK
clk => TCNTB1[9].CLK
clk => TCNTB1[8].CLK
clk => TCNTB1[7].CLK
clk => TCNTB1[6].CLK
clk => TCNTB1[5].CLK
clk => TCNTB1[4].CLK
clk => TCNTB1[3].CLK
clk => TCNTB1[2].CLK
clk => TCNTB1[1].CLK
clk => TCNTB1[0].CLK
clk => TCMPB1[15].CLK
clk => TCMPB1[14].CLK
clk => TCMPB1[13].CLK
clk => TCMPB1[12].CLK
clk => TCMPB1[11].CLK
clk => TCMPB1[10].CLK
clk => TCMPB1[9].CLK
clk => TCMPB1[8].CLK
clk => TCMPB1[7].CLK
clk => TCMPB1[6].CLK
clk => TCMPB1[5].CLK
clk => TCMPB1[4].CLK
clk => TCMPB1[3].CLK
clk => TCMPB1[2].CLK
clk => TCMPB1[1].CLK
clk => TCMPB1[0].CLK
clk => TCNT1[15].CLK
clk => TCNT1[14].CLK
clk => TCNT1[13].CLK
clk => TCNT1[12].CLK
clk => TCNT1[11].CLK
clk => TCNT1[10].CLK
clk => TCNT1[9].CLK
clk => TCNT1[8].CLK
clk => TCNT1[7].CLK
clk => TCNT1[6].CLK
clk => TCNT1[5].CLK
clk => TCNT1[4].CLK
clk => TCNT1[3].CLK
clk => TCNT1[2].CLK
clk => TCNT1[1].CLK
clk => TCNT1[0].CLK
clk => TCMP1[15].CLK
clk => TCMP1[14].CLK
clk => TCMP1[13].CLK
clk => TCMP1[12].CLK
clk => TCMP1[11].CLK
clk => TCMP1[10].CLK
clk => TCMP1[9].CLK
clk => TCMP1[8].CLK
clk => TCMP1[7].CLK
clk => TCMP1[6].CLK
clk => TCMP1[5].CLK
clk => TCMP1[4].CLK
clk => TCMP1[3].CLK
clk => TCMP1[2].CLK
clk => TCMP1[1].CLK
clk => TCMP1[0].CLK
clk => TDEADZONE[15].CLK
clk => TDEADZONE[14].CLK
clk => TDEADZONE[13].CLK
clk => TDEADZONE[12].CLK
clk => TDEADZONE[11].CLK
clk => TDEADZONE[10].CLK
clk => TDEADZONE[9].CLK
clk => TDEADZONE[8].CLK
clk => TDEADZONE[7].CLK
clk => TDEADZONE[6].CLK
clk => TDEADZONE[5].CLK
clk => TDEADZONE[4].CLK
clk => TDEADZONE[3].CLK
clk => TDEADZONE[2].CLK
clk => TDEADZONE[1].CLK
clk => TDEADZONE[0].CLK
clk => TCNTB2[15].CLK
clk => TCNTB2[14].CLK
clk => TCNTB2[13].CLK
clk => TCNTB2[12].CLK
clk => TCNTB2[11].CLK
clk => TCNTB2[10].CLK
clk => TCNTB2[9].CLK
clk => TCNTB2[8].CLK
clk => TCNTB2[7].CLK
clk => TCNTB2[6].CLK
clk => TCNTB2[5].CLK
clk => TCNTB2[4].CLK
clk => TCNTB2[3].CLK
clk => TCNTB2[2].CLK
clk => TCNTB2[1].CLK
clk => TCNTB2[0].CLK
clk => TCMPB2[15].CLK
clk => TCMPB2[14].CLK
clk => TCMPB2[13].CLK
clk => TCMPB2[12].CLK
clk => TCMPB2[11].CLK
clk => TCMPB2[10].CLK
clk => TCMPB2[9].CLK
clk => TCMPB2[8].CLK
clk => TCMPB2[7].CLK
clk => TCMPB2[6].CLK
clk => TCMPB2[5].CLK
clk => TCMPB2[4].CLK
clk => TCMPB2[3].CLK
clk => TCMPB2[2].CLK
clk => TCMPB2[1].CLK
clk => TCMPB2[0].CLK
clk => TCNT2[15].CLK
clk => TCNT2[14].CLK
clk => TCNT2[13].CLK
clk => TCNT2[12].CLK
clk => TCNT2[11].CLK
clk => TCNT2[10].CLK
clk => TCNT2[9].CLK
clk => TCNT2[8].CLK
clk => TCNT2[7].CLK
clk => TCNT2[6].CLK
clk => TCNT2[5].CLK
clk => TCNT2[4].CLK
clk => TCNT2[3].CLK
clk => TCNT2[2].CLK
clk => TCNT2[1].CLK
clk => TCNT2[0].CLK
clk => TCMP2[15].CLK
clk => TCMP2[14].CLK
clk => TCMP2[13].CLK
clk => TCMP2[12].CLK
clk => TCMP2[11].CLK
clk => TCMP2[10].CLK
clk => TCMP2[9].CLK
clk => TCMP2[8].CLK
clk => TCMP2[7].CLK
clk => TCMP2[6].CLK
clk => TCMP2[5].CLK
clk => TCMP2[4].CLK
clk => TCMP2[3].CLK
clk => TCMP2[2].CLK
clk => TCMP2[1].CLK
clk => TCMP2[0].CLK
clk => deadcount1[7].CLK
clk => deadcount1[6].CLK
clk => deadcount1[5].CLK
clk => deadcount1[4].CLK
clk => deadcount1[3].CLK
clk => deadcount1[2].CLK
clk => deadcount1[1].CLK
clk => deadcount1[0].CLK
clk => deadcount2[7].CLK
clk => deadcount2[6].CLK
clk => deadcount2[5].CLK
clk => deadcount2[4].CLK
clk => deadcount2[3].CLK
clk => deadcount2[2].CLK
clk => deadcount2[1].CLK
clk => deadcount2[0].CLK
clk => data[15]~en.CLK
clk => data[15]~reg0.CLK
clk => data[14]~en.CLK
clk => data[14]~reg0.CLK
clk => data[13]~en.CLK
clk => data[13]~reg0.CLK
clk => data[12]~en.CLK
clk => data[12]~reg0.CLK
clk => data[11]~en.CLK
clk => data[11]~reg0.CLK
clk => data[10]~en.CLK
clk => data[10]~reg0.CLK
clk => data[9]~en.CLK
clk => data[9]~reg0.CLK
clk => data[8]~en.CLK
clk => data[8]~reg0.CLK
clk => data[7]~en.CLK
clk => data[7]~reg0.CLK
clk => data[6]~en.CLK
clk => data[6]~reg0.CLK
clk => data[5]~en.CLK
clk => data[5]~reg0.CLK
clk => data[4]~en.CLK
clk => data[4]~reg0.CLK
clk => data[3]~en.CLK
clk => data[3]~reg0.CLK
clk => data[2]~en.CLK
clk => data[2]~reg0.CLK
clk => data[1]~en.CLK
clk => data[1]~reg0.CLK
clk => data[0]~en.CLK
clk => data[0]~reg0.CLK
clk => pwmout1.CLK
clk => deadpwmout1.CLK
clk => out1~reg0.CLK
clk => out2~reg0.CLK
clk => pwmout2.CLK
clk => deadpwmout2.CLK
clk => out3~reg0.CLK
clk => out4~reg0.CLK
cs => process0~0.IN0
cs => process0~8.IN0
oe => process0~1.IN0
oe => process0~8.IN1
we => process0~9.IN1
we => process0~0.IN1
addr[0] => Equal5.IN15
addr[0] => Equal4.IN15
addr[0] => Equal3.IN15
addr[0] => Equal2.IN15
addr[0] => Equal1.IN15
addr[0] => Equal0.IN15
addr[1] => Equal5.IN14
addr[1] => Equal4.IN14
addr[1] => Equal3.IN14
addr[1] => Equal2.IN14
addr[1] => Equal1.IN14
addr[1] => Equal0.IN14
addr[2] => Equal5.IN13
addr[2] => Equal4.IN13
addr[2] => Equal3.IN13
addr[2] => Equal2.IN13
addr[2] => Equal1.IN13
addr[2] => Equal0.IN13
addr[3] => Equal5.IN12
addr[3] => Equal4.IN12
addr[3] => Equal3.IN12
addr[3] => Equal2.IN12
addr[3] => Equal1.IN12
addr[3] => Equal0.IN12
addr[4] => Equal5.IN11
addr[4] => Equal4.IN11
addr[4] => Equal3.IN11
addr[4] => Equal2.IN11
addr[4] => Equal1.IN11
addr[4] => Equal0.IN11
addr[5] => Equal5.IN10
addr[5] => Equal4.IN10
addr[5] => Equal3.IN10
addr[5] => Equal2.IN10
addr[5] => Equal1.IN10
addr[5] => Equal0.IN10
addr[6] => Equal5.IN9
addr[6] => Equal4.IN9
addr[6] => Equal3.IN9
addr[6] => Equal2.IN9
addr[6] => Equal1.IN9
addr[6] => Equal0.IN9
addr[7] => Equal5.IN8
addr[7] => Equal4.IN8
addr[7] => Equal3.IN8
addr[7] => Equal2.IN8
addr[7] => Equal1.IN8
addr[7] => Equal0.IN8
data[0] <= data[0]~5
data[1] <= data[1]~16
data[2] <= data[2]~22
data[3] <= data[3]~28
data[4] <= data[4]~34
data[5] <= data[5]~40
data[6] <= data[6]~46
data[7] <= data[7]~52
data[8] <= data[8]~58
data[9] <= data[9]~64
data[10] <= data[10]~70
data[11] <= data[11]~76
data[12] <= data[12]~82
data[13] <= data[13]~88
data[14] <= data[14]~94
data[15] <= data[15]~100
out1 <= out1~reg0.DB_MAX_OUTPUT_PORT_TYPE
out2 <= out2~reg0.DB_MAX_OUTPUT_PORT_TYPE
out3 <= out3~reg0.DB_MAX_OUTPUT_PORT_TYPE
out4 <= out4~reg0.DB_MAX_OUTPUT_PORT_TYPE
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