fredivn.vhd.bak

VHDL写的PWM发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fredivn is
	GENERIC (N: integer := 8);
	port(
		clk :		in std_logic;
		out_clk :	out std_logic
		);
end fredivn;
architecture behave of fredivn iS
	signal  count : integer range 0 to N-1;
begin
	process(clk) 
	begin
		if(clk'event and clk = '1') then
			count <= count + 1;
			if(count < integer(N/2)) then
				outclk <= '0';
			else
				outclk <= '1';
			end if;
		end if;
	end process;
end behave;