multi4.vhd

用VHDL写的4*4乘法器

-----------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fulladd1 IS
port(
	A : in std_logic;
	B : in std_logic;
	cin1 : in std_logic;
	cout1 : out std_logic;
	C : out std_logic
     );
end fulladd1;

architecture add1 of fulladd1 is
begin
	C <= A XOR B XOR cin1;
	cout1 <= (A AND B) OR (A AND cin1) OR (B AND cin1);
end add1;

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fulladd4 IS
PORT(
	in1 :IN std_logic_vector(3 downto 0);
	in2 :IN std_logic_vector(3 downto 0);
	cin :IN std_logic;
	cout:OUT std_logic;
	OUT1:OUT std_logic_vector(3 downto 0)
     );
END fulladd4;

architecture add4 of fulladd4 is
 component fulladd1
	port(	
		A : in std_logic;
		B : in std_logic;
		cin1 : in std_logic;
		cout1 : out std_logic;
		C : out std_logic
     	     );
 end component;
SIGNAL T : std_logic_vector( 2 downto 0 );
begin 
      u1:fulladd1 port map(in1(0),in2(0),cin,T(0),OUT1(0));
      u2:fulladd1 port map(in1(1),in2(1),T(0),T(1),OUT1(1));
      u3:fulladd1 port map(in1(2),in2(2),T(1),T(2),OUT1(2));  
      u4:fulladd1 port map(in1(3),in2(3),T(2),cout,OUT1(3));
end add4;

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LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY xb IS           
PORT ( A : IN std_logic_vector( 3 downto 0) ;
       B : IN std_logic;
       XB : BUFFER std_logic_vector( 3 downto 0) );
END xb;

ARCHITECTURE xb_bit OF xb IS 
BEGIN
	XB(0) <= A(0) AND B;
	XB(1) <= A(1) AND B;
	XB(2) <= A(2) AND B;
	XB(3) <= A(3) AND B;
END xb_bit;
------------------------------------------------


LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY multi4 IS          --4位乘法
PORT ( MA, MB : IN std_logic_vector( 3 downto 0 );
       P : OUT std_logic_vector( 7 downto 0 ) );
END multi4;


architecture m4 of multi4  is
        component fulladd4
	PORT(
		in1 :IN std_logic_vector(3 downto 0);
		in2 :IN std_logic_vector(3 downto 0);
		cin :IN std_logic;
		cout:OUT std_logic;
		OUT1:OUT std_logic_vector(3 downto 0)
     	     );
        END component;

	COMPONENT xb 
    	PORT ( A : IN std_logic_vector( 3 downto 0) ;
          	 B : IN std_logic;
          	 XB : BUFFER std_logic_vector( 3 downto 0) );
  	END COMPONENT;

  SIGNAL addA, addB, addC, addD, TEMP , NN : std_logic_vector( 3 downto 0 );
  SIGNAL TA, TB, TC, TD : std_logic_vector( 3 downto 0 );
  SIGNAL CO : std_logic_vector ( 3 downto 0 );
begin 
    		x1 : xb port map ( MA, MB(0), addA );
		x2 : xb port map ( MA, MB(1), addB );
		x3 : xb port map ( MA, MB(2), addC );
		x4 : xb port map ( MA, MB(3), addD );
		p(0)<=addA(0);
		TA(0) <= addA(1);
		TA(1) <= addA(2);
		TA(2) <= addA(3);
		TA(3) <= '0';
		CO(0) <= '0';
		ad1 : fulladd4 port map ( addB, TA,CO(0),CO(1), TEMP );
		P(1) <= TEMP(0) ;
		TB(0) <= TEMP(1);
		TB(1) <= TEMP(2);
		TB(2) <= TEMP(3);
		TB(3) <= CO(1);
		ad2 : fulladd4 port map ( addC, TB, CO(0), CO(2), NN);
		P(2) <=  NN(0) ;
		TC(0) <= NN(1);
		TC(1) <= NN(2);
		TC(2) <= NN(3);
		TC(3) <= CO(2);
		ad3 : fulladd4 port map ( addD, TC, CO(0), CO(3) ,TD);
		P(3) <= TD(0);
		P(4) <= TD(1);
		P(5) <= TD(2);
		P(6) <= TD(3);
		P(7) <= CO(3);
END m4;