_primary.vhd

来自「針對通訊中的dsb系統做硬體模擬的實現與驗證希忘的大家有一定的幫助謝謝」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity mul_cordic is
    generic(
        din_size        : integer := 12
    );
    port(
        din_I           : in     vl_logic_vector;
        din_Q           : in     vl_logic_vector;
        phase_in        : in     vl_logic_vector(13 downto 0);
        clk_system      : in     vl_logic;
        en_in           : in     vl_logic;
        frame_start     : in     vl_logic;
        dout_I          : out    vl_logic_vector;
        dout_Q          : out    vl_logic_vector;
        en_out          : out    vl_logic;
        frame_start_out : out    vl_logic
    );
end mul_cordic;