speaker.map.rpt

用VHDL语言仿真歌曲刘德华的《月老》

; WIDTHAD_A                          ; 8                                    ; Integer               ;
; NUMWORDS_A                         ; 256                                  ; Integer               ;
; OUTDATA_REG_A                      ; CLOCK0                               ; Untyped               ;
; ADDRESS_ACLR_A                     ; NONE                                 ; Untyped               ;
; OUTDATA_ACLR_A                     ; NONE                                 ; Untyped               ;
; WRCONTROL_ACLR_A                   ; NONE                                 ; Untyped               ;
; INDATA_ACLR_A                      ; NONE                                 ; Untyped               ;
; BYTEENA_ACLR_A                     ; NONE                                 ; Untyped               ;
; WIDTH_B                            ; 1                                    ; Untyped               ;
; WIDTHAD_B                          ; 1                                    ; Untyped               ;
; NUMWORDS_B                         ; 1                                    ; Untyped               ;
; INDATA_REG_B                       ; CLOCK1                               ; Untyped               ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                               ; Untyped               ;
; RDCONTROL_REG_B                    ; CLOCK1                               ; Untyped               ;
; ADDRESS_REG_B                      ; CLOCK1                               ; Untyped               ;
; OUTDATA_REG_B                      ; UNREGISTERED                         ; Untyped               ;
; BYTEENA_REG_B                      ; CLOCK1                               ; Untyped               ;
; INDATA_ACLR_B                      ; NONE                                 ; Untyped               ;
; WRCONTROL_ACLR_B                   ; NONE                                 ; Untyped               ;
; ADDRESS_ACLR_B                     ; NONE                                 ; Untyped               ;
; OUTDATA_ACLR_B                     ; NONE                                 ; Untyped               ;
; RDCONTROL_ACLR_B                   ; NONE                                 ; Untyped               ;
; BYTEENA_ACLR_B                     ; NONE                                 ; Untyped               ;
; WIDTH_BYTEENA_A                    ; 1                                    ; Integer               ;
; WIDTH_BYTEENA_B                    ; 1                                    ; Untyped               ;
; RAM_BLOCK_TYPE                     ; AUTO                                 ; Untyped               ;
; BYTE_SIZE                          ; 8                                    ; Untyped               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                            ; Untyped               ;
; INIT_FILE                          ; D:/eda设计/VHDL/音乐演奏/speaker.mif ; Untyped               ;
; INIT_FILE_LAYOUT                   ; PORT_A                               ; Untyped               ;
; MAXIMUM_DEPTH                      ; 0                                    ; Untyped               ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                               ; Untyped               ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                               ; Untyped               ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                               ; Untyped               ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                               ; Untyped               ;
; DEVICE_FAMILY                      ; Cyclone                              ; Untyped               ;
; CBXI_PARAMETER                     ; altsyncram_kiq                       ; Untyped               ;
+------------------------------------+--------------------------------------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/eda设计/VHDL/月老/speaker.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Dec 04 20:26:42 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off speaker -c speaker
Info: Found 2 design units, including 1 entities, in source file speaker.vhd
    Info: Found design unit 1: speaker-one
    Info: Found entity 1: speaker
Info: Found 2 design units, including 1 entities, in source file tonetaba.vhd
    Info: Found design unit 1: tonetaba-one
    Info: Found entity 1: tonetaba
Info: Found 2 design units, including 1 entities, in source file notetabs.vhd
    Info: Found design unit 1: notetabs-one
    Info: Found entity 1: notetabs
Info: Found 2 design units, including 1 entities, in source file songer.vhd
    Info: Found design unit 1: songer-one
    Info: Found entity 1: songer
Info: Elaborating entity "songer" for the top level hierarchy
Info: Elaborating entity "notetabs" for hierarchy "notetabs:u1"
Warning: VHDL Process Statement warning at notetabs.vhd(18): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Using design file music.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: music-SYN
    Info: Found entity 1: music
Info: Elaborating entity "music" for hierarchy "notetabs:u1|music:u1"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "notetabs:u1|music:u1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kiq.tdf
    Info: Found entity 1: altsyncram_kiq
Info: Elaborating entity "altsyncram_kiq" for hierarchy "notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated"
Info: Elaborating entity "tonetaba" for hierarchy "tonetaba:u2"
Warning: VHDL Process Statement warning at tonetaba.vhd(9): signal or variable "tone" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "tone" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "speaker" for hierarchy "speaker:u3"
Info: Duplicate registers merged to single register
    Info: Duplicate register "speaker:u3|spks" merged to single register "speaker:u3|\delayspks:count2"
Warning: Latch tonetaba:u2|tone[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[3]
Warning: Latch tonetaba:u2|tone[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[0]
Warning: Latch tonetaba:u2|tone[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1]
Info: Implemented 64 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 57 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Tue Dec 04 20:26:44 2007
    Info: Elapsed time: 00:00:03