speaker.tan.qmsg

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[8\] " "Info: Node \"tonetaba:u2\|tone\[8\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[1\] " "Info: Node \"tonetaba:u2\|tone\[1\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[0\] " "Info: Node \"tonetaba:u2\|tone\[0\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk12MHZ " "Info: Assuming node \"clk12MHZ\" is an undefined clock" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/songer.vhd" 4 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk12MHZ" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk8HZ " "Info: Assuming node \"clk8HZ\" is an undefined clock" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/songer.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk8HZ" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "speaker:u3\|\\divideclk:count4\[2\] " "Info: Detected ripple clock \"speaker:u3\|\\divideclk:count4\[2\]\" as buffer" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|\\divideclk:count4\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "speaker:u3\|\\divideclk:count4\[3\] " "Info: Detected ripple clock \"speaker:u3\|\\divideclk:count4\[3\]\" as buffer" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|\\divideclk:count4\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "speaker:u3\|LessThan~40 " "Info: Detected gated clock \"speaker:u3\|LessThan~40\" as buffer" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|LessThan~40" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "speaker:u3\|fullspks " "Info: Detected ripple clock \"speaker:u3\|fullspks\" as buffer" {  } { { "speaker.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/speaker.vhd" 10 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|fullspks" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk12MHZ register speaker:u3\|\\genspks:count11\[10\] register speaker:u3\|\\genspks:count11\[10\] 229.25 MHz 4.362 ns Internal " "Info: Clock \"clk12MHZ\" has Internal fmax of 229.25 MHz between source register \"speaker:u3\|\\genspks:count11\[10\]\" and destination register \"speaker:u3\|\\genspks:count11\[10\]\" (period= 4.362 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.014 ns + Longest register register " "Info: + Longest register to register delay is 4.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speaker:u3\|\\genspks:count11\[10\] 1 REG LC_X10_Y7_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y7_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.965 ns) + CELL(0.340 ns) 1.305 ns speaker:u3\|reduce_nor~70 2 COMB LC_X10_Y8_N2 2 " "Info: 2: + IC(0.965 ns) + CELL(0.340 ns) = 1.305 ns; Loc. = LC_X10_Y8_N2; Fanout = 2; COMB Node = 'speaker:u3\|reduce_nor~70'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "1.305 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.454 ns) 2.102 ns speaker:u3\|reduce_nor~71 3 COMB LC_X10_Y8_N0 11 " "Info: 3: + IC(0.343 ns) + CELL(0.454 ns) = 2.102 ns; Loc. = LC_X10_Y8_N0; Fanout = 11; COMB Node = 'speaker:u3\|reduce_nor~71'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "0.797 ns" { speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.969 ns) + CELL(0.943 ns) 4.014 ns speaker:u3\|\\genspks:count11\[10\] 4 REG LC_X10_Y7_N5 2 " "Info: 4: + IC(0.969 ns) + CELL(0.943 ns) = 4.014 ns; Loc. = LC_X10_Y7_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "1.912 ns" { speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 43.27 % " "Info: Total cell delay = 1.737 ns ( 43.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.277 ns 56.73 % " "Info: Total interconnect delay = 2.277 ns ( 56.73 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "4.014 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.014 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } { 0.000ns 0.965ns 0.343ns 0.969ns } { 0.000ns 0.340ns 0.454ns 0.943ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.146 ns - Smallest " "Info: - Smallest clock skew is -0.146 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12MHZ destination 6.192 ns + Shortest register " "Info: + Shortest clock path from clock \"clk12MHZ\" to destination register is 6.192 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'clk12MHZ'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { clk12MHZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/songer.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.720 ns) 2.279 ns speaker:u3\|\\divideclk:count4\[2\] 2 REG LC_X8_Y6_N6 3 " "Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N6; Fanout = 3; REG Node = 'speaker:u3\|\\divideclk:count4\[2\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "1.149 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.088 ns) 2.786 ns speaker:u3\|LessThan~40 3 COMB LC_X8_Y6_N5 16 " "Info: 3: + IC(0.419 ns) + CELL(0.088 ns) = 2.786 ns; Loc. = LC_X8_Y6_N5; Fanout = 16; COMB Node = 'speaker:u3\|LessThan~40'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "0.507 ns" { speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.859 ns) + CELL(0.547 ns) 6.192 ns speaker:u3\|\\genspks:count11\[10\] 4 REG LC_X10_Y7_N5 2 " "Info: 4: + IC(2.859 ns) + CELL(0.547 ns) = 6.192 ns; Loc. = LC_X10_Y7_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "3.406 ns" { speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.485 ns 40.13 % " "Info: Total cell delay = 2.485 ns ( 40.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.707 ns 59.87 % " "Info: Total interconnect delay = 3.707 ns ( 59.87 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "6.192 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.192 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.429ns 0.419ns 2.859ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12MHZ source 6.338 ns - Longest register " "Info: - Longest clock path from clock \"clk12MHZ\" to source register is 6.338 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'clk12MHZ'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { clk12MHZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/songer.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.720 ns) 2.279 ns speaker:u3\|\\divideclk:count4\[3\] 2 REG LC_X8_Y6_N4 2 " "Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N4; Fanout = 2; REG Node = 'speaker:u3\|\\divideclk:count4\[3\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "1.149 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.225 ns) 2.932 ns speaker:u3\|LessThan~40 3 COMB LC_X8_Y6_N5 16 " "Info: 3: + IC(0.428 ns) + CELL(0.225 ns) = 2.932 ns; Loc. = LC_X8_Y6_N5; Fanout = 16; COMB Node = 'speaker:u3\|LessThan~40'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "0.653 ns" { speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.859 ns) + CELL(0.547 ns) 6.338 ns speaker:u3\|\\genspks:count11\[10\] 4 REG LC_X10_Y7_N5 2 " "Info: 4: + IC(2.859 ns) + CELL(0.547 ns) = 6.338 ns; Loc. = LC_X10_Y7_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "3.406 ns" { speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 41.37 % " "Info: Total cell delay = 2.622 ns ( 41.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.716 ns 58.63 % " "Info: Total interconnect delay = 3.716 ns ( 58.63 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "6.338 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.338 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.429ns 0.428ns 2.859ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0}  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "6.192 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.192 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.429ns 0.419ns 2.859ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } } { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "6.338 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.338 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.429ns 0.428ns 2.859ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } {  } 0}  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "4.014 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.014 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } { 0.000ns 0.965ns 0.343ns 0.969ns } { 0.000ns 0.340ns 0.454ns 0.943ns } } } { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "6.192 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.192 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.429ns 0.419ns 2.859ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } } { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "6.338 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.338 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.429ns 0.428ns 2.859ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0}