speaker.hier_info

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计

|songer
clk12MHZ => speaker:u3.clk
clk8HZ => notetabs:u1.clk
spkout <= speaker:u3.spks


|songer|notetabs:u1
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => music:u1.clock
clk => counter[7].CLK
toneindex[0] <= music:u1.q[0]
toneindex[1] <= music:u1.q[1]
toneindex[2] <= music:u1.q[2]
toneindex[3] <= music:u1.q[3]


|songer|notetabs:u1|music:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]


|songer|notetabs:u1|music:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_e1q:auto_generated.address_a[0]
address_a[1] => altsyncram_e1q:auto_generated.address_a[1]
address_a[2] => altsyncram_e1q:auto_generated.address_a[2]
address_a[3] => altsyncram_e1q:auto_generated.address_a[3]
address_a[4] => altsyncram_e1q:auto_generated.address_a[4]
address_a[5] => altsyncram_e1q:auto_generated.address_a[5]
address_a[6] => altsyncram_e1q:auto_generated.address_a[6]
address_a[7] => altsyncram_e1q:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_e1q:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_e1q:auto_generated.q_a[0]
q_a[1] <= altsyncram_e1q:auto_generated.q_a[1]
q_a[2] <= altsyncram_e1q:auto_generated.q_a[2]
q_a[3] <= altsyncram_e1q:auto_generated.q_a[3]
q_b[0] <= <GND>


|songer|notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT


|songer|tonetaba:u2
index[0] => Mux~0.IN16
index[0] => Mux~1.IN19
index[0] => Mux~2.IN16
index[0] => Mux~3.IN16
index[0] => Mux~4.IN16
index[0] => Mux~5.IN16
index[0] => Mux~6.IN16
index[0] => Mux~7.IN16
index[0] => Mux~8.IN16
index[0] => Mux~9.IN16
index[0] => Mux~10.IN16
index[0] => Mux~11.IN16
index[1] => Mux~0.IN15
index[1] => Mux~1.IN18
index[1] => Mux~2.IN15
index[1] => Mux~3.IN15
index[1] => Mux~4.IN15
index[1] => Mux~5.IN15
index[1] => Mux~6.IN15
index[1] => Mux~7.IN15
index[1] => Mux~8.IN15
index[1] => Mux~9.IN15
index[1] => Mux~10.IN15
index[1] => Mux~11.IN15
index[2] => Mux~0.IN14
index[2] => Mux~1.IN17
index[2] => Mux~2.IN14
index[2] => Mux~3.IN14
index[2] => Mux~4.IN14
index[2] => Mux~5.IN14
index[2] => Mux~6.IN14
index[2] => Mux~7.IN14
index[2] => Mux~8.IN14
index[2] => Mux~9.IN14
index[2] => Mux~10.IN14
index[2] => Mux~11.IN14
index[3] => Mux~0.IN13
index[3] => Mux~1.IN16
index[3] => Mux~2.IN13
index[3] => Mux~3.IN13
index[3] => Mux~4.IN13
index[3] => Mux~5.IN13
index[3] => Mux~6.IN13
index[3] => Mux~7.IN13
index[3] => Mux~8.IN13
index[3] => Mux~9.IN13
index[3] => Mux~10.IN13
index[3] => Mux~11.IN13
tone[0] <= tone[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[1] <= tone[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[2] <= tone[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[3] <= tone[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[4] <= tone[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[5] <= tone[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[6] <= tone[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[7] <= tone[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[8] <= tone[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[9] <= tone[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
tone[10] <= tone[10]$latch.DB_MAX_OUTPUT_PORT_TYPE


|songer|speaker:u3
clk => \divideclk:count4[2].CLK
clk => \divideclk:count4[1].CLK
clk => \divideclk:count4[0].CLK
clk => \divideclk:count4[3].CLK
tone[0] => count11~10.DATAB
tone[1] => count11~9.DATAB
tone[2] => count11~8.DATAB
tone[3] => count11~7.DATAB
tone[4] => count11~6.DATAB
tone[5] => count11~5.DATAB
tone[6] => count11~4.DATAB
tone[7] => count11~3.DATAB
tone[8] => count11~2.DATAB
tone[9] => count11~1.DATAB
tone[10] => count11~0.DATAB
spks <= spks~reg0.DB_MAX_OUTPUT_PORT_TYPE