speaker.fit.rpt

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计

; 9                                          ; 0                            ;
; 10                                         ; 4                            ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 0.58) ; Number of LABs  (Total = 12) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 1                            ;
; 1 Clock                            ; 5                            ;
; 1 Sync. load                       ; 1                            ;
+------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Signals Sourced                                                        ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 4.75) ; Number of LABs  (Total = 12) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 5                            ;
; 2                                           ; 1                            ;
; 3                                           ; 0                            ;
; 4                                           ; 1                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 0                            ;
; 8                                           ; 0                            ;
; 9                                           ; 0                            ;
; 10                                          ; 3                            ;
; 11                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 3.00) ; Number of LABs  (Total = 12) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 6                            ;
; 2                                               ; 2                            ;
; 3                                               ; 1                            ;
; 4                                               ; 0                            ;
; 5                                               ; 0                            ;
; 6                                               ; 1                            ;
; 7                                               ; 0                            ;
; 8                                               ; 1                            ;
; 9                                               ; 1                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 4.00) ; Number of LABs  (Total = 12) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 7                            ;
; 3                                           ; 1                            ;
; 4                                           ; 1                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 0                            ;
; 8                                           ; 0                            ;
; 9                                           ; 0                            ;
; 10                                          ; 1                            ;
; 11                                          ; 0                            ;
; 12                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Nov 26 20:05:14 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off speaker -c speaker
Info: Selected device EP1C3T144C6 for design "speaker"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C6T144C6 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk8HZ" to use Global clock in PIN 17
Info: Automatically promoted signal "clk12MHZ" to use Global clock in PIN 92
Info: Automatically promoted signal "speaker:u3|LessThan~40" to use Global clock
Info: Automatically promoted signal "tonetaba:u2|Mux~303" to use Global clock
Info: Automatically promoted signal "notetabs:u1|reduce_nor~0" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is memory to memory delay of 3.323 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|ram_block1a1~porta_address_reg0'
    Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X13_Y8; Fanout = 13; MEM Node = 'notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|q_a[1]'
    Info: Total cell delay = 3.323 ns ( 100.00 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%.
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Nov 26 20:05:23 2007
    Info: Elapsed time: 00:00:09