speaker.map.summary

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计

Flow Status : Successful - Mon Nov 26 20:05:12 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : speaker
Top-level Entity Name : songer
Family : Cyclone
Device : EP1C3T144C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 57
Total pins : 3
Total virtual pins : 0
Total memory bits : 1,024
Total PLLs : 0