speaker.tan.summary

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.030 ns
From           : speaker:u3|\delayspks:count2
To             : spkout
From Clock     : clk12MHZ
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk12MHZ'
Slack          : N/A
Required Time  : None
Actual Time    : 229.25 MHz ( period = 4.362 ns )
From           : speaker:u3|\genspks:count11[10]
To             : speaker:u3|\genspks:count11[8]
From Clock     : clk12MHZ
To Clock       : clk12MHZ
Failed Paths   : 0

Type           : Clock Setup: 'clk8HZ'
Slack          : N/A
Required Time  : None
Actual Time    : 256.02 MHz ( period = 3.906 ns )
From           : notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|ram_block1a1~porta_address_reg7
To             : notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|q_a[1]
From Clock     : clk8HZ
To Clock       : clk8HZ
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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