light.fit.qmsg

用VHDL语言仿真交通灯 用VHDL语言仿真交通灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 22:08:46 2007 " "Info: Processing started: Sat Dec 08 22:08:46 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off light -c light " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off light -c light" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "light EP1C3T144C6 " "Info: Selected device EP1C3T144C6 for design \"light\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C6 " "Info: Device EP1C6T144C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 17 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 17" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted signal \"rst\" to use Global clock" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { rst } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/红绿灯/light.fld" "" { Floorplan "D:/eda设计/VHDL/红绿灯/light.fld" "" "" { rst } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.272 ns register register " "Info: Estimated most critical path is register to register delay of 2.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time\[2\] 1 REG LAB_X2_Y1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y1; Fanout = 4; REG Node = 'time\[2\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { time[2] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.454 ns) 0.570 ns reduce_nor~114 2 COMB LAB_X2_Y1 1 " "Info: 2: + IC(0.116 ns) + CELL(0.454 ns) = 0.570 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'reduce_nor~114'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.570 ns" { time[2] reduce_nor~114 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.286 ns) + CELL(0.225 ns) 1.081 ns reduce_nor~0 3 COMB LAB_X2_Y1 8 " "Info: 3: + IC(0.286 ns) + CELL(0.225 ns) = 1.081 ns; Loc. = LAB_X2_Y1; Fanout = 8; COMB Node = 'reduce_nor~0'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.511 ns" { reduce_nor~114 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.856 ns) 2.272 ns time\[1\] 4 REG LAB_X2_Y1 4 " "Info: 4: + IC(0.335 ns) + CELL(0.856 ns) = 2.272 ns; Loc. = LAB_X2_Y1; Fanout = 4; REG Node = 'time\[1\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "1.191 ns" { reduce_nor~0 time[1] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns 67.56 % " "Info: Total cell delay = 1.535 ns ( 67.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.737 ns 32.44 % " "Info: Total interconnect delay = 0.737 ns ( 32.44 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.272 ns" { time[2] reduce_nor~114 reduce_nor~0 time[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 22:08:48 2007 " "Info: Processing ended: Sat Dec 08 22:08:48 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}