📄 light.fit.rpt
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; time[0]~78COUT1_86 ; 1 ;
; time[0]~78 ; 1 ;
; time[2]~74COUT1_87 ; 1 ;
; time[2]~74 ; 1 ;
; time[1]~66COUT1 ; 1 ;
; time[1]~66 ; 1 ;
+----------------------+----------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 4 / 8,840 ( < 1 % ) ;
; Direct links ; 0 / 11,506 ( 0 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; LAB clocks ; 2 / 156 ( 1 % ) ;
; LUT chains ; 0 / 2,619 ( 0 % ) ;
; Local interconnects ; 4 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 3 / 7,520 ( < 1 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 10.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+---------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 1 ;
; 1 Clock ; 1 ;
+------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 3.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 2.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Dec 08 22:08:46 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off light -c light
Info: Selected device EP1C3T144C6 for design "light"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C6 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 2.272 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y1; Fanout = 4; REG Node = 'time[2]'
Info: 2: + IC(0.116 ns) + CELL(0.454 ns) = 0.570 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'reduce_nor~114'
Info: 3: + IC(0.286 ns) + CELL(0.225 ns) = 1.081 ns; Loc. = LAB_X2_Y1; Fanout = 8; COMB Node = 'reduce_nor~0'
Info: 4: + IC(0.335 ns) + CELL(0.856 ns) = 2.272 ns; Loc. = LAB_X2_Y1; Fanout = 4; REG Node = 'time[1]'
Info: Total cell delay = 1.535 ns ( 67.56 % )
Info: Total interconnect delay = 0.737 ns ( 32.44 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Dec 08 22:08:48 2007
Info: Elapsed time: 00:00:03
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