topcounter.v

来自「利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综」· Verilog 代码 · 共 28 行

module topcounter (
	aload,
	clock,
	data,
	sclr,
	sload,
	q);

	input	  aload;
	input	  clock;
	input	[19:0]  data;
	input	  sclr;
	output	  sload;
	output	[19:0]  q;
	
	counter mycounter(
	.aload(aload),
	.clock(clock),
	.data(data),
	.sclr(sclr),
	.sload(sload),
	.q(q));
	
	myand thisand(
	.datain(q),
	.out(sload));
	
	endmodule