📄 clock_main.rpt
字号:
61 94 F FF + t 0 0 0 0 1 0 4 SEL6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock_050509\clock_main.rpt
clock_main
** BURIED LOGIC **
Shareable
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 1 A TFFE t 3 0 0 0 4 1 7 |clock_clock:155|7490:1|QA (|clock_clock:155|7490:1|:7)
(62) 96 F DFFE t 0 0 0 0 3 0 7 |clock_clock:155|7490:1|QB (|clock_clock:155|7490:1|:11)
- 114 H TFFE t 0 0 0 0 2 0 4 |clock_clock:155|7490:1|QC (|clock_clock:155|7490:1|:14)
(75) 118 H DFFE t 0 0 0 0 3 1 5 |clock_clock:155|7490:1|QD (|clock_clock:155|7490:1|:19)
(12) 3 A TFFE t 1 0 0 0 4 1 5 |clock_clock:155|7490:21|QA (|clock_clock:155|7490:21|:7)
(15) 29 B DFFE t 0 0 0 0 3 0 5 |clock_clock:155|7490:21|QB (|clock_clock:155|7490:21|:11)
(14) 32 B TFFE t 0 0 0 0 2 0 3 |clock_clock:155|7490:21|QC (|clock_clock:155|7490:21|:14)
- 20 B DFFE t 0 0 0 0 3 1 5 |clock_clock:155|7490:21|QD (|clock_clock:155|7490:21|:19)
(77) 123 H TFFE t 0 0 0 0 1 1 4 |clock_clock:155|7492:2|QA (|clock_clock:155|7492:2|:7)
(73) 115 H DFFE t 0 0 0 0 3 0 4 |clock_clock:155|7492:2|QB (|clock_clock:155|7492:2|:11)
(79) 125 H DFFE t 0 0 0 0 2 1 4 |clock_clock:155|7492:2|QC (|clock_clock:155|7492:2|:14)
- 52 D TFFE t 0 0 0 0 1 1 4 |clock_clock:155|7492:20|QA (|clock_clock:155|7492:20|:7)
- 90 F DFFE t 0 0 0 0 3 0 5 |clock_clock:155|7492:20|QB (|clock_clock:155|7492:20|:11)
- 89 F DFFE t 0 0 0 0 2 1 7 |clock_clock:155|7492:20|QC (|clock_clock:155|7492:20|:14)
(40) 51 D DFFE t 3 3 0 0 9 0 7 |clock_clock:155|74161:48|p74161:sub|QD (|clock_clock:155|74161:48|p74161:sub|:6)
- 50 D DFFE t 4 3 1 0 9 0 8 |clock_clock:155|74161:48|p74161:sub|QC (|clock_clock:155|74161:48|p74161:sub|:7)
(36) 57 D DFFE t 3 3 0 0 9 0 5 |clock_clock:155|74161:48|p74161:sub|QB (|clock_clock:155|74161:48|p74161:sub|:8)
- 54 D TFFE t 3 3 0 0 6 0 8 |clock_clock:155|74161:48|p74161:sub|QA (|clock_clock:155|74161:48|p74161:sub|:9)
- 82 F TFFE t 1 1 0 0 5 0 8 |clock_clock:155|74161:49|p74161:sub|QB (|clock_clock:155|74161:49|p74161:sub|:8)
- 84 F TFFE t 1 1 0 0 4 0 3 |clock_clock:155|74161:49|p74161:sub|QA (|clock_clock:155|74161:49|p74161:sub|:9)
(50) 75 E TFFE t 0 0 0 0 3 0 7 |clock_ring:95|7490:16|QA (|clock_ring:95|7490:16|:7)
- 127 H DFFE t 0 0 0 0 3 0 7 |clock_ring:95|7490:16|QB (|clock_ring:95|7490:16|:11)
- 124 H TFFE t 0 0 0 0 2 0 4 |clock_ring:95|7490:16|QC (|clock_ring:95|7490:16|:14)
(81) 128 H DFFE t 0 0 0 0 3 0 5 |clock_ring:95|7490:16|QD (|clock_ring:95|7490:16|:19)
- 78 E TFFE t 0 0 0 0 3 0 5 |clock_ring:95|7490:17|QA (|clock_ring:95|7490:17|:7)
- 22 B DFFE t 0 0 0 0 3 0 5 |clock_ring:95|7490:17|QB (|clock_ring:95|7490:17|:11)
(18) 24 B TFFE t 0 0 0 0 2 0 3 |clock_ring:95|7490:17|QC (|clock_ring:95|7490:17|:14)
(17) 25 B DFFE t 0 0 0 0 3 0 5 |clock_ring:95|7490:17|QD (|clock_ring:95|7490:17|:19)
- 92 F TFFE t 0 0 0 0 1 0 4 |clock_ring:95|7492:14|QA (|clock_ring:95|7492:14|:7)
- 28 B DFFE t 0 0 0 0 3 0 4 |clock_ring:95|7492:14|QB (|clock_ring:95|7492:14|:11)
(16) 27 B DFFE t 0 0 0 0 2 0 3 |clock_ring:95|7492:14|QC (|clock_ring:95|7492:14|:14)
(22) 17 B TFFE t 0 0 0 0 1 0 4 |clock_ring:95|7492:15|QA (|clock_ring:95|7492:15|:7)
(20) 21 B DFFE t 0 0 0 0 3 0 5 |clock_ring:95|7492:15|QB (|clock_ring:95|7492:15|:11)
- 23 B DFFE t 0 0 0 0 2 0 3 |clock_ring:95|7492:15|QC (|clock_ring:95|7492:15|:14)
- 70 E TFFE t 1 1 0 0 5 0 8 |clock_ring:95|74161:1|p74161:sub|QB (|clock_ring:95|74161:1|p74161:sub|:8)
- 68 E TFFE t 1 1 0 0 4 0 3 |clock_ring:95|74161:1|p74161:sub|QA (|clock_ring:95|74161:1|p74161:sub|:9)
- 79 E DFFE t 1 1 0 0 8 0 7 |clock_ring:95|74161:2|p74161:sub|QD (|clock_ring:95|74161:2|p74161:sub|:6)
- 76 E DFFE t 2 1 1 0 8 0 8 |clock_ring:95|74161:2|p74161:sub|QC (|clock_ring:95|74161:2|p74161:sub|:7)
- 66 E DFFE t 1 1 0 0 8 0 5 |clock_ring:95|74161:2|p74161:sub|QB (|clock_ring:95|74161:2|p74161:sub|:8)
- 71 E TFFE t 1 1 0 0 5 0 8 |clock_ring:95|74161:2|p74161:sub|QA (|clock_ring:95|74161:2|p74161:sub|:9)
- 95 F DFFE + t 0 0 0 0 1 0 1 |clock_s:96|:38
- 33 C DFFE + t 0 0 0 0 1 0 23 |clock_s:96|:39
- 63 D DFFE t 0 0 0 1 4 0 27 |clock_s:96|:40
- 81 F TFFE t 0 0 0 0 1 0 22 |clock_s:96|:43
(21) 19 B DFFE + t 0 0 0 0 1 0 1 |clock_s:96|:55
(5) 14 A TFFE t 3 3 0 1 4 0 4 |clock_s:96|7490:28|QA (|clock_s:96|7490:28|:7)
(24) 46 C DFFE t 3 3 0 0 7 0 4 |clock_s:96|7490:28|QB (|clock_s:96|7490:28|:11)
- 42 C TFFE t 3 3 0 0 6 0 2 |clock_s:96|7490:28|QC (|clock_s:96|7490:28|:14)
(25) 45 C DFFE t 3 3 0 0 7 0 3 |clock_s:96|7490:28|QD (|clock_s:96|7490:28|:19)
- 36 C TFFE t 3 3 0 0 5 0 4 |clock_s:96|7490:29|QA (|clock_s:96|7490:29|:7)
(64) 99 G DFFE t 3 3 0 0 7 0 4 |clock_s:96|7490:29|QB (|clock_s:96|7490:29|:11)
(65) 101 G TFFE t 3 3 0 0 6 0 2 |clock_s:96|7490:29|QC (|clock_s:96|7490:29|:14)
- 108 G DFFE t 3 3 0 0 7 0 3 |clock_s:96|7490:29|QD (|clock_s:96|7490:29|:19)
- 39 C TFFE t 3 3 0 0 5 0 4 |clock_s:96|7490:30|QA (|clock_s:96|7490:30|:7)
- 100 G DFFE t 3 3 0 0 7 0 4 |clock_s:96|7490:30|QB (|clock_s:96|7490:30|:11)
- 111 G TFFE t 3 3 0 0 6 0 2 |clock_s:96|7490:30|QC (|clock_s:96|7490:30|:14)
- 110 G DFFE t 3 3 0 0 7 0 3 |clock_s:96|7490:30|QD (|clock_s:96|7490:30|:19)
(35) 59 D TFFE t 3 3 0 0 5 0 4 |clock_s:96|7490:31|QA (|clock_s:96|7490:31|:7)
(67) 104 G DFFE t 3 3 0 0 7 0 4 |clock_s:96|7490:31|QB (|clock_s:96|7490:31|:11)
(71) 112 G TFFE t 3 3 0 0 6 0 2 |clock_s:96|7490:31|QC (|clock_s:96|7490:31|:14)
(70) 109 G DFFE t 3 3 0 0 7 0 3 |clock_s:96|7490:31|QD (|clock_s:96|7490:31|:19)
- 15 A TFFE t 3 3 0 0 5 0 3 |clock_s:96|7492:27|QA (|clock_s:96|7492:27|:7)
- 103 G DFFE t 3 3 0 0 7 0 3 |clock_s:96|7492:27|QB (|clock_s:96|7492:27|:11)
- 98 G DFFE t 3 3 0 0 6 0 3 |clock_s:96|7492:27|QC (|clock_s:96|7492:27|:14)
(33) 64 D TFFE t 3 3 0 0 5 0 3 |clock_s:96|7492:34|QA (|clock_s:96|7492:34|:7)
- 44 C DFFE t 3 3 0 0 7 0 3 |clock_s:96|7492:34|QB (|clock_s:96|7492:34|:11)
- 47 C DFFE t 3 3 0 0 6 0 2 |clock_s:96|7492:34|QC (|clock_s:96|7492:34|:14)
- 58 D TFFE + t 2 2 0 1 4 0 1 |clock_s:96|74161:44|p74161:sub|QD (|clock_s:96|74161:44|p74161:sub|:6)
- 60 D TFFE + t 2 2 0 1 3 0 2 |clock_s:96|74161:44|p74161:sub|QC (|clock_s:96|74161:44|p74161:sub|:7)
(37) 56 D TFFE + t 2 2 0 1 2 0 3 |clock_s:96|74161:44|p74161:sub|QB (|clock_s:96|74161:44|p74161:sub|:8)
- 55 D TFFE + t 2 2 0 1 1 0 4 |clock_s:96|74161:44|p74161:sub|QA (|clock_s:96|74161:44|p74161:sub|:9)
(76) 120 H SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~1
(4) 16 A SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~2
- 18 B SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~3
- 30 B SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~4
- 31 B SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~5
- 62 D SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~6
- 119 H SOFT s t 1 0 1 0 6 0 1 |COMP:134|~143~7
(10) 6 A DFFE t 0 0 0 1 2 3 2 :25
- 87 F SOFT s t 15 0 1 0 18 5 0 ~63~4~1~2
(74) 117 H DFFE t 14 9 0 0 17 0 1 :135
- 122 H DFFE t 9 9 0 0 12 1 2 :149
- 116 H DFFE t 0 0 0 1 2 0 2 :178
- 121 H DFFE t 0 0 0 1 2 0 13 INC (:179)
- 9 A DFFE t 0 0 0 1 2 0 3 :180
- 4 A DFFE t 0 0 0 1 2 1 2 :189
- 113 H DFFE t 0 0 0 1 2 3 2 :206
(80) 126 H TFFE t 0 0 0 1 0 0 1 :228
(68) 105 G TFFE t 0 0 0 0 1 1 2 :229
- 26 B SOFT s t 13 0 0 0 20 7 0 |7448:57|~25~1
- 102 G SOFT s t 1 0 1 0 12 0 1 |7448:57|~25~2
- 74 E SOFT s t 13 0 0 0 22 7 0 |7448:57|~27~1
- 106 G SOFT s t 1 0 1 0 12 0 1 |7448:57|~27~2
(30) 37 C SOFT s t 13 0 0 0 22 7 0 |7448:57|~29~1
(63) 97 G SOFT s t 1 0 1 0 12 0 1 |7448:57|~29~2
- 12 A TFFE + t 2 2 0 1 2 0 1 |74161:31|p74161:sub|QB (|74161:31|p74161:sub|:8)
(6) 13 A TFFE + t 2 2 0 1 1 0 2 |74161:31|p74161:sub|QA (|74161:31|p74161:sub|:9)
(9) 8 A TFFE + t 2 2 0 1 2 0 1 |74161:174|p74161:sub|QB (|74161:174|p74161:sub|:8)
(8) 11 A TFFE + t 2 2 0 1 1 0 2 |74161:174|p74161:sub|QA (|74161:174|p74161:sub|:9)
(11) 5 A TFFE + t 2 2 0 1 2 0 1 |74161:190|p74161:sub|QB (|74161:190|p74161:sub|:8)
- 2 A TFFE + t 2 2 0 1 1 0 2 |74161:190|p74161:sub|QA (|74161:190|p74161:sub|:9)
- 7 A TFFE + t 2 2 0 1 2 0 1 |74161:199|p74161:sub|QB (|74161:199|p74161:sub|:8)
- 10 A TFFE + t 2 2 0 1 1 0 2 |74161:199|p74161:sub|QA (|74161:199|p74161:sub|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock_050509\clock_main.rpt
clock_main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC1 |clock_clock:155|7490:1|QA
| +----------------------------- LC3 |clock_clock:155|7490:21|QA
| | +--------------------------- LC14 |clock_s:96|7490:28|QA
| | | +------------------------- LC15 |clock_s:96|7492:27|QA
| | | | +----------------------- LC16 |COMP:134|~143~2
| | | | | +--------------------- LC6 :25
| | | | | | +------------------- LC9 :180
| | | | | | | +----------------- LC4 :189
| | | | | | | | +--------------- LC12 |74161:31|p74161:sub|QB
| | | | | | | | | +------------- LC13 |74161:31|p74161:sub|QA
| | | | | | | | | | +----------- LC8 |74161:174|p74161:sub|QB
| | | | | | | | | | | +--------- LC11 |74161:174|p74161:sub|QA
| | | | | | | | | | | | +------- LC5 |74161:190|p74161:sub|QB
| | | | | | | | | | | | | +----- LC2 |74161:190|p74161:sub|QA
| | | | | | | | | | | | | | +--- LC7 |74161:199|p74161:sub|QB
| | | | | | | | | | | | | | | +- LC10 |74161:199|p74161:sub|QA
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC6 -> - - - - - - - - * * - - - - - - | * - - - * - - - | <-- :25
LC9 -> - - - - - - - - - - * * - - - - | * - - - - - - * | <-- :180
LC4 -> - - - - - - - - - - - - * * - - | * - - - - - * - | <-- :189
LC12 -> - - - - - * - - * - - - - - - - | * - - - - - - - | <-- |74161:31|p74161:sub|QB
LC13 -> - - - - - * - - * * - - - - - - | * - - - - - - - | <-- |74161:31|p74161:sub|QA
LC8 -> - - - - - - * - - - * - - - - - | * - - - - - - - | <-- |74161:174|p74161:sub|QB
LC11 -> - - - - - - * - - - * * - - - - | * - - - - - - - | <-- |74161:174|p74161:sub|QA
LC5 -> - - - - - - - * - - - - * - - - | * - - - - - - - | <-- |74161:190|p74161:sub|QB
LC2 -> - - - - - - - * - - - - * * - - | * - - - - - - - | <-- |74161:190|p74161:sub|QA
LC10 -> - - - - - - - - - - - - - - * * | * - - - - - - * | <-- |74161:199|p74161:sub|QA
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- C128Hz
2 -> - - * - - - - - - - - - - - - - | * - - - - * - - | <-- C1024Hz
4 -> - - - - - - - - - - - - - - * * | * - - - - - - * | <-- LOCATION_SEL
8 -> - - - - - - - * - - - - * * - - | * - - - - - - - | <-- RING_ON_OFF
65 -> - - - - - * - - * * - - - - - - | * - - - - - - - | <-- SEL_FUNCTION
5 -> - - - - - - * - - - * * - - - - | * - - - - - - - | <-- UP
LC125-> - * - - - - - - - - - - - - - - | * * - - - * - * | <-- |clock_clock:155|7492:2|QC
LC50 -> - - - - * - - - - - - - - - - - | * * - * - * - - | <-- |clock_clock:155|74161:48|p74161:sub|QC
LC57 -> - - - - * - - - - - - - - - - - | * - - * * - - - | <-- |clock_clock:155|74161:48|p74161:sub|QB
LC54 -> - - - - * - - - - - - - - - - - | * - * * - * - * | <-- |clock_clock:155|74161:48|p74161:sub|QA
LC76 -> - - - - * - - - - - - - - - - - | * * - - * - - - | <-- |clock_ring:95|74161:2|p74161:sub|QC
LC66 -> - - - - * - - - - - - - - - - - | * - - - * - - - | <-- |clock_ring:95|74161:2|p74161:sub|QB
LC71 -> - - - - * - - - - - - - - - - - | * - * - * - - * | <-- |clock_ring:95|74161:2|p74161:sub|QA
LC33 -> - - * * - - - - - - - - - - - - | * - * * - * * - | <-- |clock_s:96|:39
LC63 -> - - * * - - - - - - - - - - - - | * - * * - - * - | <-- |clock_s:96|:40
LC81 -> - - * * - - - - - - - - - - - - | * - * * - - * - | <-- |clock_s:96|:43
LC108-> - - - * - - - - - - - - - - - - | * - - - - * * - | <-- |clock_s:96|7490:29|QD
LC65 -> * * - - - - - - - - - - - - - - | * - - * * - - - | <-- SEL_CORR
LC67 -> - * - - - - - - - - - - - - - - | * - - - * - - - | <-- SEL_M
LC77 -> * - - - - - - - - - - - - - - - | * - - - * - - - | <-- SEL_S
LC73 -> - - * * - - - - - - - - - - - - | * * * * * * * - | <-- SEL_S_CLOCK
LC121-> * * - - - - - - - - - - - - - - | * - - * * - - * | <-- INC
LC113-> - - - - - - - - - - - - - - * * | * - - - * - - - | <-- :206
LC105-> * - - - - - - - - - - - - - - - | * - - - - * - * | <-- :229
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock_050509\clock_main.rpt
clock_main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
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