📄 clock_clock.rpt
字号:
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------------------- LC59 H102
| +------------------------- LC55 M1
| | +----------------------- LC54 M2
| | | +--------------------- LC53 M3
| | | | +------------------- LC52 M100
| | | | | +----------------- LC51 M101
| | | | | | +--------------- LC50 M102
| | | | | | | +------------- LC60 RING_ZD
| | | | | | | | +----------- LC58 S1
| | | | | | | | | +--------- LC64 S2
| | | | | | | | | | +------- LC62 S3
| | | | | | | | | | | +----- LC61 S100
| | | | | | | | | | | | +--- LC57 S101
| | | | | | | | | | | | | +- LC49 S102
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC55 -> - * * * - - - - - - - - - - | - - - * | <-- M1
LC54 -> - - * * - - - - - - - - - - | - - - * | <-- M2
LC53 -> - * - - * - - * - - - - - - | - - - * | <-- M3
LC52 -> - - - - * * * * - - - - - - | - - - * | <-- M100
LC51 -> - - - - - * * - - - - - - - | - - - * | <-- M101
LC50 -> - - - - - * - * - - - - - - | - - * * | <-- M102
LC58 -> - - - - - - - - * * * - - - | - - - * | <-- S1
LC64 -> - - - - - - - - - * * - - - | - - - * | <-- S2
LC62 -> - - - - - - - * * - - * - - | - - - * | <-- S3
LC61 -> - - - - - - - * - - - * * * | - - - * | <-- S100
LC57 -> - - - - - - - - - - - - * * | - - - * | <-- S101
LC49 -> - - - - - - - * - - - - * - | - - * * | <-- S102
Pin
15 -> - - - - - - - * - - - - - - | - - - * | <-- C512Hz
12 -> - - - - - - - * - - - - - - | - - - * | <-- C1024Hz
LC33 -> - * * * - - - * - - - - - - | - - - * | <-- M0
LC39 -> - - - - - - - * * * * - - - | - - - * | <-- S0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
** EQUATIONS **
C1Hz : INPUT;
C512Hz : INPUT;
C1024Hz : INPUT;
SEL_CORR : INPUT;
SEL_H : INPUT;
SEL_M : INPUT;
SEL_S : INPUT;
UP : INPUT;
-- Node name is 'H0' = '|74161:48|p74161:sub|QA'
-- Equation name is 'H0', type is output
H0 = TFFE( VCC, _EQ001, !_EQ002, VCC, VCC);
_EQ001 = _X001 & _X002 & _X003;
_X001 = EXP(!M102 & !SEL_H);
_X002 = EXP(!M102 & !SEL_CORR);
_X003 = EXP(!M102 & !UP);
_EQ002 = H2 & H101;
-- Node name is 'H1' = '|74161:48|p74161:sub|QB'
-- Equation name is 'H1', type is output
H1 = DFFE( _EQ003 $ GND, _EQ004, !_EQ005, VCC, VCC);
_EQ003 = H0 & !H1 & !H3
# !H0 & H1;
_EQ004 = _X001 & _X002 & _X003;
_X001 = EXP(!M102 & !SEL_H);
_X002 = EXP(!M102 & !SEL_CORR);
_X003 = EXP(!M102 & !UP);
_EQ005 = H2 & H101;
-- Node name is 'H2' = '|74161:48|p74161:sub|QC'
-- Equation name is 'H2', type is output
H2 = DFFE( _EQ006 $ GND, _EQ007, !_EQ008, VCC, VCC);
_EQ006 = H0 & H1 & !H2 & !H3
# !H1 & H2 & !H3
# !H0 & H2;
_EQ007 = _X001 & _X002 & _X003;
_X001 = EXP(!M102 & !SEL_H);
_X002 = EXP(!M102 & !SEL_CORR);
_X003 = EXP(!M102 & !UP);
_EQ008 = H2 & H101;
-- Node name is 'H3' = '|74161:48|p74161:sub|QD'
-- Equation name is 'H3', type is output
H3 = DFFE( _EQ009 $ GND, _EQ010, !_EQ011, VCC, VCC);
_EQ009 = H0 & H1 & H2 & !H3
# !H0 & H3;
_EQ010 = _X001 & _X002 & _X003;
_X001 = EXP(!M102 & !SEL_H);
_X002 = EXP(!M102 & !SEL_CORR);
_X003 = EXP(!M102 & !UP);
_EQ011 = H2 & H101;
-- Node name is 'H100' = '|74161:49|p74161:sub|QA'
-- Equation name is 'H100', type is output
H100 = TFFE( VCC, _EQ012, !_EQ013, VCC, VCC);
_EQ012 = _X004;
_X004 = EXP( H0 & H3);
_EQ013 = H2 & H101;
-- Node name is 'H101' = '|74161:49|p74161:sub|QB'
-- Equation name is 'H101', type is output
H101 = TFFE( H100, _EQ014, !_EQ015, VCC, VCC);
_EQ014 = _X004;
_X004 = EXP( H0 & H3);
_EQ015 = H2 & H101;
-- Node name is 'H102'
-- Equation name is 'H102', location is LC059, type is output.
H102 = LCELL( GND $ GND);
-- Node name is 'H103'
-- Equation name is 'H103', location is LC041, type is output.
H103 = LCELL( GND $ GND);
-- Node name is 'M0' = '|7490:21|QA'
-- Equation name is 'M0', type is output
M0 = TFFE( VCC, _EQ016, VCC, VCC, VCC);
_EQ016 = !S102 & _X005;
_X005 = EXP( SEL_CORR & SEL_M & UP);
-- Node name is 'M1' = '|7490:21|QB'
-- Equation name is 'M1', type is output
M1 = DFFE( _EQ017 $ GND, !M0, VCC, VCC, VCC);
_EQ017 = !M1 & !M3;
-- Node name is 'M2' = '|7490:21|QC'
-- Equation name is 'M2', type is output
M2 = TFFE( M1, !M0, VCC, VCC, VCC);
-- Node name is 'M3' = '|7490:21|QD'
-- Equation name is 'M3', type is output
M3 = DFFE( _EQ018 $ GND, !M0, VCC, VCC, VCC);
_EQ018 = M1 & M2;
-- Node name is 'M100' = '|7492:20|QA'
-- Equation name is 'M100', type is output
M100 = TFFE( VCC, !M3, VCC, VCC, VCC);
-- Node name is 'M101' = '|7492:20|QB'
-- Equation name is 'M101', type is output
M101 = DFFE( _EQ019 $ GND, !M100, VCC, VCC, VCC);
_EQ019 = !M101 & !M102;
-- Node name is 'M102' = '|7492:20|QC'
-- Equation name is 'M102', type is output
M102 = DFFE( M101 $ GND, !M100, VCC, VCC, VCC);
-- Node name is 'M103'
-- Equation name is 'M103', location is LC042, type is output.
M103 = LCELL( GND $ GND);
-- Node name is 'RING_ZD'
-- Equation name is 'RING_ZD', location is LC060, type is output.
RING_ZD = LCELL( _EQ020 $ GND);
_EQ020 = C1024Hz & M0 & M3 & M100 & M102 & S0 & S3 & S100 & S102
# C512Hz & M0 & M3 & M100 & M102 & S0 & !S3 & S100 & S102;
-- Node name is 'S0' = '|7490:1|QA'
-- Equation name is 'S0', type is output
S0 = TFFE( VCC, _EQ021, VCC, VCC, VCC);
_EQ021 = _X006 & _X007 & _X008;
_X006 = EXP(!C1Hz & !UP);
_X007 = EXP(!C1Hz & !SEL_CORR);
_X008 = EXP(!C1Hz & !SEL_S);
-- Node name is 'S1' = '|7490:1|QB'
-- Equation name is 'S1', type is output
S1 = DFFE( _EQ022 $ GND, !S0, VCC, VCC, VCC);
_EQ022 = !S1 & !S3;
-- Node name is 'S2' = '|7490:1|QC'
-- Equation name is 'S2', type is output
S2 = TFFE( S1, !S0, VCC, VCC, VCC);
-- Node name is 'S3' = '|7490:1|QD'
-- Equation name is 'S3', type is output
S3 = DFFE( _EQ023 $ GND, !S0, VCC, VCC, VCC);
_EQ023 = S1 & S2;
-- Node name is 'S100' = '|7492:2|QA'
-- Equation name is 'S100', type is output
S100 = TFFE( VCC, !S3, VCC, VCC, VCC);
-- Node name is 'S101' = '|7492:2|QB'
-- Equation name is 'S101', type is output
S101 = DFFE( _EQ024 $ GND, !S100, VCC, VCC, VCC);
_EQ024 = !S101 & !S102;
-- Node name is 'S102' = '|7492:2|QC'
-- Equation name is 'S102', type is output
S102 = DFFE( S101 $ GND, !S100, VCC, VCC, VCC);
-- Node name is 'S103'
-- Equation name is 'S103', location is LC043, type is output.
S103 = LCELL( GND $ GND);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\gongzuo\digital clock\clock_clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,590K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -