📄 clock_main.rpt
字号:
|busmux:123|lpm_mux:40|muxlut:102|
|busmux:118|
|busmux:118|lpm_mux:40|
|busmux:118|lpm_mux:40|altshift:external_latency_ffs|
|busmux:118|lpm_mux:40|muxlut:57|
|busmux:118|lpm_mux:40|muxlut:72|
|busmux:118|lpm_mux:40|muxlut:87|
|busmux:118|lpm_mux:40|muxlut:102|
|comp:134|
|clock_clock:155|
|clock_clock:155|7490:21|
|clock_clock:155|7490:146|
|clock_clock:155|7490:1|
|clock_clock:155|7492:20|
|clock_clock:155|7492:2|
|clock_clock:155|74161:49|
|clock_clock:155|74161:49|p74161:sub|
|7448:234|
Device-Specific Information:d:\gongzuo\clock\digital clock_050610\clock_main.rpt
clock_main
***** Logic for device 'clock_main' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = ON
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = ON
Device-Specific Information:d:\gongzuo\clock\digital clock_050610\clock_main.rpt
clock_main
** ERROR SUMMARY **
Info: Chip 'clock_main' in device 'EPM7128SLC84-15' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
L
R O
S I C
T N A
R A R G T R R R R R R
E R E _ I C E E E E E E
S T S O O V 1 C S S S S S S
E _ E N N C 0 1 E E E V E E E
R S R _ C _ C 2 2 R R R C R R R
V T V O G 4 S I 4 G G 8 G V V V C V V V
E O E F N H U E N H N N H N E E E I E E E
D P D F D z P L T z D D z D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | RESERVED
RESERVED | 17 69 | RING_ON
RESERVED | 18 68 | RESERVED
GND | 19 67 | RESERVED
C512Hz | 20 66 | VCCIO
RESERVED | 21 65 | SEL_FUNCTION
RESERVED | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | SEL6
VCCIO | 26 60 | RING_OUT
d | 27 59 | GND
c | 28 58 | SEL5
b | 29 57 | SEL3
RESERVED | 30 56 | SEL2
e | 31 55 | SEL4
GND | 32 54 | RING_ZD
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R a R R R V f R g G V S S S G S S R S S V
E E E E C E N C E E E N E E E E E C
S S S S C S D C L L L D L L S L L C
E E E E I E I _ _ 1 _ _ E _ _ I
R R R R O R N C M R S R S H O
V V V V V T O I _ V
E E E E E R N C E
D D D D D R G L D
O
C
K
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:d:\gongzuo\clock\digital clock_050610\clock_main.rpt
clock_main
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 5/ 8( 62%) 15/16( 93%) 35/36( 97%)
B: LC17 - LC32 15/16( 93%) 2/ 8( 25%) 16/16(100%) 34/36( 94%)
C: LC33 - LC48 16/16(100%) 5/ 8( 62%) 16/16(100%) 35/36( 97%)
D: LC49 - LC64 16/16(100%) 3/ 8( 37%) 4/16( 25%) 25/36( 69%)
E: LC65 - LC80 16/16(100%) 7/ 8( 87%) 16/16(100%) 35/36( 97%)
F: LC81 - LC96 16/16(100%) 8/ 8(100%) 14/16( 87%) 36/36(100%)
G: LC97 - LC112 16/16(100%) 3/ 8( 37%) 8/16( 50%) 35/36( 97%)
H: LC113 - LC128 15/16( 93%) 0/ 8( 0%) 16/16(100%) 35/36( 97%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 33/64 ( 51%)
Total logic cells used: 126/128 ( 98%)
Total shareable expanders used: 93/128 ( 72%)
Total Turbo logic cells used: 126/128 ( 98%)
Total shareable expanders not available (n/a): 12/128 ( 9%)
Average fan-in: 5.33
Total fan-in: 672
Total input pins required: 9
Total fast input logic cells required: 0
Total output pins required: 22
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 126
Total flipflops required: 103
Total product terms required: 415
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 88
Synthesized logic cells: 14/ 128 ( 10%)
Device-Specific Information:d:\gongzuo\clock\digital clock_050610\clock_main.rpt
clock_main
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
6 (13) (A) INPUT 0 0 0 0 0 0 3 C4Hz
83 - - INPUT G 0 0 0 0 0 0 1 C128Hz
20 (21) (B) INPUT 0 0 0 0 0 1 0 C512Hz
2 - - INPUT G 0 0 0 0 0 2 0 C1024Hz
4 (16) (A) INPUT 0 0 0 0 0 0 3 LOCATION_SEL
8 (11) (A) INPUT 0 0 0 0 0 0 3 RING_ON_OFF
65 (101) (G) INPUT 0 0 0 0 0 0 3 SEL_FUNCTION
10 (6) (A) INPUT 0 0 0 0 0 0 5 START_STOP
5 (14) (A) INPUT 0 0 0 0 0 0 3 UP
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:d:\gongzuo\clock\digital clock_050610\clock_main.rpt
clock_main
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
34 61 D OUTPUT t 0 0 0 0 4 0 0 a
29 38 C OUTPUT t 0 0 0 0 4 0 0 b
28 40 C OUTPUT t 0 0 0 0 4 0 0 c
27 43 C OUTPUT t 0 0 0 0 3 0 0 d
31 35 C OUTPUT t 0 0 0 0 3 0 0 e
39 53 D OUTPUT t 0 0 0 0 4 0 0 f
41 49 D OUTPUT t 1 0 0 0 4 0 0 g
69 107 G FF t 0 0 0 0 1 0 3 RING_ON
60 93 F OUTPUT t 0 0 0 1 2 0 0 RING_OUT
54 83 F OUTPUT t 0 0 0 2 8 0 0 RING_ZD
44 65 E FF t 0 0 0 0 4 5 3 SEL_CORR
52 80 E FF t 0 0 0 0 5 1 5 SEL_H
45 67 E FF t 0 0 0 0 5 2 2 SEL_M
48 72 E FF t 0 0 0 0 2 5 13 SEL_RING
51 77 E FF t 0 0 0 0 7 2 2 SEL_S
49 73 E FF t 0 0 0 0 2 4 29 SEL_S_CLOCK
46 69 E FF + t 0 0 0 0 5 2 7 SEL1
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