📄 clock_clock.rpt
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Project Information d:\gongzuo\digital clock\clock_clock.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/03/2005 21:18:26
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
clock_clock
EPM7064SLC84-5 8 25 0 25 8 39 %
User Pins: 8 25 0
Project Information d:\gongzuo\digital clock\clock_clock.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'H103' is stuck at GND
Warning: Primitive 'H102' is stuck at GND
Warning: Primitive 'M103' is stuck at GND
Warning: Primitive 'S103' is stuck at GND
Project Information d:\gongzuo\digital clock\clock_clock.rpt
** FILE HIERARCHY **
|7490:21|
|7490:1|
|7492:20|
|7492:2|
|74161:48|
|74161:48|p74161:sub|
|74161:49|
|74161:49|p74161:sub|
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
***** Logic for device 'clock_clock' compiled without errors.
Device: EPM7064SLC84-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R
E E E E E E E E R
S S S S S S S V S I
E E E E E E E C E V N
R R R R R R R C R C S G H
V V V V G V V V I G G G G G V C 1 _ 1
E E E E N E E E N N N N N N S E S I 0 Z 0
D D D D D D D D T D D D D D 2 D 3 O 0 D 2
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
C1024Hz | 12 74 | S1
VCCIO | 13 73 | S101
#TDI | 14 72 | GND
C512Hz | 15 71 | #TDO
UP | 16 70 | M1
SEL_S | 17 69 | M2
SEL_M | 18 68 | M3
GND | 19 67 | M100
SEL_H | 20 66 | VCCIO
SEL_CORR | 21 65 | M101
C1Hz | 22 EPM7064SLC84-5 64 | M102
#TMS | 23 63 | S102
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | RESERVED
RESERVED | 30 56 | S103
RESERVED | 31 55 | M103
GND | 32 54 | H103
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V M H H G H H H S H V
E E E E E C E E E N C 0 2 1 N 3 0 1 0 1 C
S S S S S C S S S D C 0 D 0 C
E E E E E I E E E I 0 1 I
R R R R R O R R R N O
V V V V V V V V T
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 9/16( 56%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/16( 6%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 11/16( 68%) 12/16( 75%) 9/16( 56%) 14/36( 38%)
D: LC49 - LC64 14/16( 87%) 15/16( 93%) 0/16( 0%) 16/36( 44%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 37/64 ( 57%)
Total logic cells used: 25/64 ( 39%)
Total shareable expanders used: 8/64 ( 12%)
Total Turbo logic cells used: 25/64 ( 39%)
Total shareable expanders not available (n/a): 1/64 ( 1%)
Average fan-in: 3.84
Total fan-in: 96
Total input pins required: 8
Total fast input logic cells required: 0
Total output pins required: 25
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 25
Total flipflops required: 20
Total product terms required: 64
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 8
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 (1) (A) INPUT 0 0 0 0 0 1 0 C1Hz
15 (7) (A) INPUT 0 0 0 0 0 1 0 C512Hz
12 (9) (A) INPUT 0 0 0 0 0 1 0 C1024Hz
21 (2) (A) INPUT 0 0 0 0 0 6 0 SEL_CORR
20 (3) (A) INPUT 0 0 0 0 0 4 0 SEL_H
18 (4) (A) INPUT 0 0 0 0 0 1 0 SEL_M
17 (5) (A) INPUT 0 0 0 0 0 1 0 SEL_S
16 (6) (A) INPUT 0 0 0 0 0 6 0 UP
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
49 37 C FF t 3 3 0 3 3 5 0 H0 (|74161:48|p74161:sub|:9)
52 40 C FF t 3 3 0 3 6 3 0 H1 (|74161:48|p74161:sub|:8)
45 34 C FF t 4 3 1 3 6 6 0 H2 (|74161:48|p74161:sub|:7)
48 36 C FF t 3 3 0 3 6 5 0 H3 (|74161:48|p74161:sub|:6)
46 35 C FF t 1 1 0 0 4 1 0 H100 (|74161:49|p74161:sub|:9)
50 38 C FF t 1 1 0 0 5 6 0 H101 (|74161:49|p74161:sub|:8)
75 59 D OUTPUT t 0 0 0 0 0 0 0 H102
54 41 C OUTPUT t 0 0 0 0 0 0 0 H103
44 33 C FF t 1 0 0 3 1 4 0 M0 (|7490:21|:7)
70 55 D FF t 0 0 0 0 3 3 0 M1 (|7490:21|:11)
69 54 D FF t 0 0 0 0 2 1 0 M2 (|7490:21|:14)
68 53 D FF t 0 0 0 0 3 3 0 M3 (|7490:21|:19)
67 52 D FF t 0 0 0 0 1 3 0 M100 (|7492:20|:7)
65 51 D FF t 0 0 0 0 3 2 0 M101 (|7492:20|:11)
64 50 D FF t 0 0 0 0 2 6 0 M102 (|7492:20|:14)
55 42 C OUTPUT t 0 0 0 0 0 0 0 M103
76 60 D OUTPUT t 0 0 0 2 8 0 0 RING_ZD
51 39 C FF t 3 0 0 4 0 4 0 S0 (|7490:1|:7)
74 58 D FF t 0 0 0 0 3 3 0 S1 (|7490:1|:11)
81 64 D FF t 0 0 0 0 2 1 0 S2 (|7490:1|:14)
79 62 D FF t 0 0 0 0 3 3 0 S3 (|7490:1|:19)
77 61 D FF t 0 0 0 0 1 3 0 S100 (|7492:2|:7)
73 57 D FF t 0 0 0 0 3 2 0 S101 (|7492:2|:11)
63 49 D FF t 0 0 0 0 2 3 0 S102 (|7492:2|:14)
56 43 C OUTPUT t 0 0 0 0 0 0 0 S103
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------- LC37 H0
| +------------------- LC40 H1
| | +----------------- LC34 H2
| | | +--------------- LC36 H3
| | | | +------------- LC35 H100
| | | | | +----------- LC38 H101
| | | | | | +--------- LC41 H103
| | | | | | | +------- LC33 M0
| | | | | | | | +----- LC42 M103
| | | | | | | | | +--- LC39 S0
| | | | | | | | | | +- LC43 S103
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC37 -> * * * * * * - - - - - | - - * - | <-- H0
LC40 -> - * * * - - - - - - - | - - * - | <-- H1
LC34 -> * * * * * * - - - - - | - - * - | <-- H2
LC36 -> - * * * * * - - - - - | - - * - | <-- H3
LC35 -> - - - - * * - - - - - | - - * - | <-- H100
LC38 -> * * * * * * - - - - - | - - * - | <-- H101
Pin
22 -> - - - - - - - - - * - | - - * - | <-- C1Hz
21 -> * * * * - - - * - * - | - - * - | <-- SEL_CORR
20 -> * * * * - - - - - - - | - - * - | <-- SEL_H
18 -> - - - - - - - * - - - | - - * - | <-- SEL_M
17 -> - - - - - - - - - * - | - - * - | <-- SEL_S
16 -> * * * * - - - * - * - | - - * - | <-- UP
LC50 -> * * * * - - - - - - - | - - * * | <-- M102
LC49 -> - - - - - - - * - - - | - - * * | <-- S102
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\clock_clock.rpt
clock_clock
** LOGIC CELL INTERCONNECTIONS **
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