📄 clock_ring.rpt
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Project Information d:\gongzuo\digital clock\clock_ring.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/03/2005 21:24:15
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
clock_ring
EPM7032SLC44-5 5 24 0 24 2 75 %
User Pins: 5 24 0
Project Information d:\gongzuo\digital clock\clock_ring.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'H103' is stuck at GND
Warning: Primitive 'H102' is stuck at GND
Warning: Primitive 'M103' is stuck at GND
Warning: Primitive 'S103' is stuck at GND
Project Information d:\gongzuo\digital clock\clock_ring.rpt
** FILE HIERARCHY **
|7490:17|
|7490:16|
|7492:15|
|7492:14|
|74161:2|
|74161:2|p74161:sub|
|74161:1|
|74161:1|p74161:sub|
Device-Specific Information: d:\gongzuo\digital clock\clock_ring.rpt
clock_ring
***** Logic for device 'clock_ring' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
Device-Specific Information: d:\gongzuo\digital clock\clock_ring.rpt
clock_ring
** ERROR SUMMARY **
Info: Chip 'clock_ring' in device 'EPM7032SLC44-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
S
E
L
_
R S
V G G G I G 1
M M M C N N N N N S 0
1 2 3 C D D D G D 0 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | SEL_M
SEL_S | 8 38 | #TDO
UP | 9 37 | H0
GND | 10 36 | H1
M102 | 11 35 | VCC
M101 | 12 EPM7032SLC44-5 34 | H2
#TMS | 13 33 | H3
S101 | 14 32 | #TCK
VCC | 15 31 | SEL_H
M100 | 16 30 | GND
S1 | 17 29 | H100
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
S S S S G V H M H M H
1 2 3 1 N C 1 1 1 0 1
0 0 D C 0 0 0 0
2 0 3 3 2 1
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\gongzuo\digital clock\clock_ring.rpt
clock_ring
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 12/16( 75%) 16/16(100%) 0/16( 0%) 14/36( 38%)
B: LC17 - LC32 12/16( 75%) 16/16(100%) 3/16( 18%) 11/36( 30%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 24/32 ( 75%)
Total shareable expanders used: 2/32 ( 6%)
Total Turbo logic cells used: 24/32 ( 75%)
Total shareable expanders not available (n/a): 1/32 ( 3%)
Average fan-in: 3.33
Total fan-in: 80
Total input pins required: 5
Total fast input logic cells required: 0
Total output pins required: 24
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 24
Total flipflops required: 20
Total product terms required: 56
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 2
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\gongzuo\digital clock\clock_ring.rpt
clock_ring
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 (26) (B) INPUT 0 0 0 0 0 4 0 SEL_H
39 (19) (B) INPUT 0 0 0 0 0 1 0 SEL_M
43 - - INPUT 0 0 0 0 0 6 0 SEL_RING
8 (5) (A) INPUT 0 0 0 0 0 1 0 SEL_S
9 (6) (A) INPUT 0 0 0 0 0 6 0 UP
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\clock_ring.rpt
clock_ring
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
37 21 B FF t 1 1 0 3 2 5 0 H0 (|74161:2|p74161:sub|:9)
36 22 B FF t 1 1 0 3 5 3 0 H1 (|74161:2|p74161:sub|:8)
34 23 B FF t 2 1 1 3 5 6 0 H2 (|74161:2|p74161:sub|:7)
33 24 B FF t 1 1 0 3 5 5 0 H3 (|74161:2|p74161:sub|:6)
29 27 B FF t 1 1 0 0 4 1 0 H100 (|74161:1|p74161:sub|:9)
28 28 B FF t 1 1 0 0 5 6 0 H101 (|74161:1|p74161:sub|:8)
26 30 B OUTPUT t 0 0 0 0 0 0 0 H102
24 32 B OUTPUT t 0 0 0 0 0 0 0 H103
27 29 B FF t 0 0 0 3 0 3 0 M0 (|7490:17|:7)
6 3 A FF t 0 0 0 0 3 3 0 M1 (|7490:17|:11)
5 2 A FF t 0 0 0 0 2 1 0 M2 (|7490:17|:14)
4 1 A FF t 0 0 0 0 3 2 0 M3 (|7490:17|:19)
16 11 A FF t 0 0 0 0 1 2 0 M100 (|7492:15|:7)
12 8 A FF t 0 0 0 0 3 2 0 M101 (|7492:15|:11)
11 7 A FF t 0 0 0 0 2 1 0 M102 (|7492:15|:14)
25 31 B OUTPUT t 0 0 0 0 0 0 0 M103
41 17 B FF t 0 0 0 3 0 3 0 S0 (|7490:16|:7)
17 12 A FF t 0 0 0 0 3 3 0 S1 (|7490:16|:11)
19 14 A FF t 0 0 0 0 2 1 0 S2 (|7490:16|:14)
20 15 A FF t 0 0 0 0 3 2 0 S3 (|7490:16|:19)
21 16 A FF t 0 0 0 0 1 2 0 S100 (|7492:14|:7)
14 10 A FF t 0 0 0 0 3 2 0 S101 (|7492:14|:11)
18 13 A FF t 0 0 0 0 2 1 0 S102 (|7492:14|:14)
40 18 B OUTPUT t 0 0 0 0 0 0 0 S103
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\clock_ring.rpt
clock_ring
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------------- LC3 M1
| +--------------------- LC2 M2
| | +------------------- LC1 M3
| | | +----------------- LC11 M100
| | | | +--------------- LC8 M101
| | | | | +------------- LC7 M102
| | | | | | +----------- LC12 S1
| | | | | | | +--------- LC14 S2
| | | | | | | | +------- LC15 S3
| | | | | | | | | +----- LC16 S100
| | | | | | | | | | +--- LC10 S101
| | | | | | | | | | | +- LC13 S102
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC3 -> * * * - - - - - - - - - | * - | <-- M1
LC2 -> - * * - - - - - - - - - | * - | <-- M2
LC1 -> * - - * - - - - - - - - | * - | <-- M3
LC11 -> - - - * * * - - - - - - | * - | <-- M100
LC8 -> - - - - * * - - - - - - | * - | <-- M101
LC7 -> - - - - * - - - - - - - | * - | <-- M102
LC12 -> - - - - - - * * * - - - | * - | <-- S1
LC14 -> - - - - - - - * * - - - | * - | <-- S2
LC15 -> - - - - - - * - - * - - | * - | <-- S3
LC16 -> - - - - - - - - - * * * | * - | <-- S100
LC10 -> - - - - - - - - - - * * | * - | <-- S101
LC13 -> - - - - - - - - - - * - | * - | <-- S102
Pin
43 -> - - - - - - - - - - - - | - * | <-- SEL_RING
LC29 -> * * * - - - - - - - - - | * - | <-- M0
LC17 -> - - - - - - * * * - - - | * - | <-- S0
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