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Project Information d:\gongzuo\digital clock\comp.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/28/2005 23:09:03
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
comp EPM7064SLC84-5 48 1 0 9 4 14 %
User Pins: 48 1 0
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
***** Logic for device 'comp' compiled without errors.
Device: EPM7064SLC84-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R
E E E E E
V S S S S S
B B B B B C E E E V E E
M H M S S C R R R C R R
B 1 B 1 G 1 1 1 I G G G G G V V V C V V A
M 0 H 0 N 0 0 0 N N N N N N E E E I E E S
3 0 3 2 D 2 3 2 T D D D D D D D D O D D 2
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
BM2 | 12 74 | RESERVED
VCCIO | 13 73 | AS3
#TDI | 14 72 | GND
BM1 | 15 71 | #TDO
BM0 | 16 70 | AS100
BH103 | 17 69 | RESERVED
BH100 | 18 68 | AS101
GND | 19 67 | RESERVED
BH101 | 20 66 | VCCIO
AM101 | 21 65 | RESERVED
BM101 | 22 EPM7064SLC84-5 64 | AEB
#TMS | 23 63 | RESERVED
AH3 | 24 62 | #TCK
BS0 | 25 61 | RESERVED
VCCIO | 26 60 | AS103
BS1 | 27 59 | GND
AH100 | 28 58 | AM100
AH101 | 29 57 | AM3
BS2 | 30 56 | AS102
BS3 | 31 55 | AM2
GND | 32 54 | AH0
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
A A B A A V B B B G V B B A G A A A A A V
H H S M M C H S H N C M H S N M H H S M C
1 1 1 0 1 C 0 1 1 D C 1 2 1 D 1 2 1 0 1 C
0 0 0 I 0 I 0 0 0 I
2 3 0 O 1 N 3 3 2 O
T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 16/16(100%) 1/16( 6%) 6/36( 16%)
B: LC17 - LC32 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 4/16( 25%) 15/16( 93%) 4/16( 25%) 20/36( 55%)
D: LC49 - LC64 4/16( 25%) 6/16( 37%) 8/16( 50%) 32/36( 88%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 53/64 ( 82%)
Total logic cells used: 9/64 ( 14%)
Total shareable expanders used: 4/64 ( 6%)
Total Turbo logic cells used: 9/64 ( 14%)
Total shareable expanders not available (n/a): 9/64 ( 14%)
Average fan-in: 7.11
Total fan-in: 64
Total input pins required: 48
Total fast input logic cells required: 0
Total output pins required: 1
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 9
Total flipflops required: 0
Total product terms required: 49
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 8/ 64 ( 12%)
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
54 (41) (C) INPUT 0 0 0 0 0 0 2 AH0
50 (38) (C) INPUT 0 0 0 0 0 0 1 AH1
49 (37) (C) INPUT 0 0 0 0 0 0 1 AH2
24 (31) (B) INPUT 0 0 0 0 0 0 1 AH3
28 (28) (B) INPUT 0 0 0 0 0 1 0 AH100
29 (27) (B) INPUT 0 0 0 0 0 1 0 AH101
33 (24) (B) INPUT 0 0 0 0 0 0 1 AH102
34 (23) (B) INPUT 0 0 0 0 0 0 1 AH103
36 (21) (B) INPUT 0 0 0 0 0 0 1 AM0
37 (20) (B) INPUT 0 0 0 0 0 0 1 AM1
55 (42) (C) INPUT 0 0 0 0 0 0 2 AM2
57 (44) (C) INPUT 0 0 0 0 0 0 1 AM3
58 (45) (C) INPUT 0 0 0 0 0 0 1 AM100
21 (2) (A) INPUT 0 0 0 0 0 0 2 AM101
52 (40) (C) INPUT 0 0 0 0 0 0 1 AM102
48 (36) (C) INPUT 0 0 0 0 0 0 1 AM103
51 (39) (C) INPUT 0 0 0 0 0 0 1 AS0
46 (35) (C) INPUT 0 0 0 0 0 0 1 AS1
75 (59) (D) INPUT 0 0 0 0 0 1 0 AS2
73 (57) (D) INPUT 0 0 0 0 0 1 0 AS3
70 (55) (D) INPUT 0 0 0 0 0 0 1 AS100
68 (53) (D) INPUT 0 0 0 0 0 0 1 AS101
56 (43) (C) INPUT 0 0 0 0 0 0 1 AS102
60 (46) (C) INPUT 0 0 0 0 0 0 2 AS103
39 (19) (B) INPUT 0 0 0 0 0 0 2 BH0
41 (17) (B) INPUT 0 0 0 0 0 0 1 BH1
45 (34) (C) INPUT 0 0 0 0 0 0 1 BH2
9 (12) (A) INPUT 0 0 0 0 0 0 1 BH3
18 (4) (A) INPUT 0 0 0 0 0 1 0 BH100
20 (3) (A) INPUT 0 0 0 0 0 1 0 BH101
8 (13) (A) INPUT 0 0 0 0 0 0 1 BH102
17 (5) (A) INPUT 0 0 0 0 0 0 1 BH103
16 (6) (A) INPUT 0 0 0 0 0 0 1 BM0
15 (7) (A) INPUT 0 0 0 0 0 0 1 BM1
12 (9) (A) INPUT 0 0 0 0 0 0 2 BM2
11 (10) (A) INPUT 0 0 0 0 0 0 1 BM3
10 (11) (A) INPUT 0 0 0 0 0 0 1 BM100
22 (1) (A) INPUT 0 0 0 0 0 0 2 BM101
6 (14) (A) INPUT 0 0 0 0 0 0 1 BM102
44 (33) (C) INPUT 0 0 0 0 0 0 1 BM103
25 (30) (B) INPUT 0 0 0 0 0 0 1 BS0
27 (29) (B) INPUT 0 0 0 0 0 0 1 BS1
30 (26) (B) INPUT 0 0 0 0 0 1 0 BS2
31 (25) (B) INPUT 0 0 0 0 0 1 0 BS3
35 (22) (B) INPUT 0 0 0 0 0 0 1 BS100
40 (18) (B) INPUT 0 0 0 0 0 0 1 BS101
4 (16) (A) INPUT 0 0 0 0 0 0 1 BS102
5 (15) (A) INPUT 0 0 0 0 0 0 2 BS103
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
64 50 D OUTPUT t 5 0 1 8 8 0 0 AEB
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(79) 62 D SOFT s t 1 0 1 6 0 1 0 ~143~1
(73) 57 D SOFT s t 1 0 1 6 0 1 0 ~143~2
(63) 49 D SOFT s t 1 0 1 6 0 1 0 ~143~3
(22) 1 A SOFT s t 1 0 1 6 0 1 0 ~143~4
(44) 33 C SOFT s t 1 0 1 6 0 1 0 ~143~5
(46) 35 C SOFT s t 1 0 1 6 0 1 0 ~143~6
(48) 36 C SOFT s t 1 0 1 6 0 1 0 ~143~7
(50) 38 C SOFT s t 1 0 1 6 0 1 0 ~143~8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC1 ~143~4
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D | Logic cells that feed LAB 'A':
Pin
21 -> * | * - - * | <-- AM101
52 -> * | * - - - | <-- AM102
48 -> * | * - - - | <-- AM103
22 -> * | * - - * | <-- BM101
6 -> * | * - - - | <-- BM102
44 -> * | * - - - | <-- BM103
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------- LC33 ~143~5
| +----- LC35 ~143~6
| | +--- LC36 ~143~7
| | | +- LC38 ~143~8
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'C'
LC | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
36 -> * - - - | - - * - | <-- AM0
37 -> * - - - | - - * - | <-- AM1
55 -> * * - - | - - * - | <-- AM2
57 -> - * - - | - - * - | <-- AM3
51 -> - - - * | - - * - | <-- AS0
46 -> - - - * | - - * - | <-- AS1
70 -> - * - - | - - * - | <-- AS100
68 -> - - * - | - - * - | <-- AS101
56 -> - - * - | - - * - | <-- AS102
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