comp.v

使用EPM7128设计的数字钟

module COMP(AS,AS10,AM,AM10,AH,AH10,BS,BS10,BM,BM10,BH,BH10,AEB);

input  [3:0] AS,AS10,AM,AM10,AH,AH10,BS,BS10,BM,BM10,BH,BH10;
output AEB;


assign  AEB=((AS==BS)? 1 : 0) && ((AS10==BS10)? 1 :0) && ((AM==BM)? 1 : 0) && ((AM10==BM10)? 1 :0) && 
            ((AH==BH)? 1 : 0) && ((AH10==BH10)? 1 :0);

endmodule