📄 clock_s.rpt
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-- Node name is 'M2' = '|7490:29|QC'
-- Equation name is 'M2', type is output
M2 = TFFE( M1, !M0, !_EQ014, VCC, VCC);
_EQ014 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'M3' = '|7490:29|QD'
-- Equation name is 'M3', type is output
M3 = DFFE( _EQ015 $ GND, !M0, !_EQ016, VCC, VCC);
_EQ015 = M1 & M2;
_EQ016 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'M100' = '|7492:27|QA'
-- Equation name is 'M100', type is output
M100 = TFFE( VCC, !M3, !_EQ017, VCC, VCC);
_EQ017 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'M101' = '|7492:27|QB'
-- Equation name is 'M101', type is output
M101 = DFFE( _EQ018 $ GND, !M100, !_EQ019, VCC, VCC);
_EQ018 = !M101 & !M102;
_EQ019 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'M102' = '|7492:27|QC'
-- Equation name is 'M102', type is output
M102 = DFFE( M101 $ GND, !M100, !_EQ020, VCC, VCC);
_EQ020 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'M103'
-- Equation name is 'M103', location is LC064, type is output.
M103 = LCELL( GND $ GND);
-- Node name is 'S0' = '|7490:28|QA'
-- Equation name is 'S0', type is output
S0 = TFFE( VCC, _EQ021, !_EQ022, VCC, VCC);
_EQ021 = !C1024Hz & _LC056;
_EQ022 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S1' = '|7490:28|QB'
-- Equation name is 'S1', type is output
S1 = DFFE( _EQ023 $ GND, !S0, !_EQ024, VCC, VCC);
_EQ023 = !S1 & !S3;
_EQ024 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S2' = '|7490:28|QC'
-- Equation name is 'S2', type is output
S2 = TFFE( S1, !S0, !_EQ025, VCC, VCC);
_EQ025 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S3' = '|7490:28|QD'
-- Equation name is 'S3', type is output
S3 = DFFE( _EQ026 $ GND, !S0, !_EQ027, VCC, VCC);
_EQ026 = S1 & S2;
_EQ027 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S100' = '|7490:30|QA'
-- Equation name is 'S100', type is output
S100 = TFFE( VCC, !S3, !_EQ028, VCC, VCC);
_EQ028 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S101' = '|7490:30|QB'
-- Equation name is 'S101', type is output
S101 = DFFE( _EQ029 $ GND, !S100, !_EQ030, VCC, VCC);
_EQ029 = !S101 & !S103;
_EQ030 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S102' = '|7490:30|QC'
-- Equation name is 'S102', type is output
S102 = TFFE( S101, !S100, !_EQ031, VCC, VCC);
_EQ031 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'S103' = '|7490:30|QD'
-- Equation name is 'S103', type is output
S103 = DFFE( _EQ032 $ GND, !S100, !_EQ033, VCC, VCC);
_EQ032 = S101 & S102;
_EQ033 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is '|74161:44|p74161:sub|:9' = '|74161:44|p74161:sub|QA'
-- Equation name is '_LC050', type is buried
_LC050 = TFFE( VCC, GLOBAL( C1024Hz), !_EQ034, VCC, VCC);
_EQ034 = _X004 & _X005;
_X004 = EXP(!_LC054 & !STAR_STOP);
_X005 = EXP( _LC054 & STAR_STOP);
-- Node name is '|74161:44|p74161:sub|:8' = '|74161:44|p74161:sub|QB'
-- Equation name is '_LC061', type is buried
_LC061 = TFFE( _LC050, GLOBAL( C1024Hz), !_EQ035, VCC, VCC);
_EQ035 = _X004 & _X005;
_X004 = EXP(!_LC054 & !STAR_STOP);
_X005 = EXP( _LC054 & STAR_STOP);
-- Node name is '|74161:44|p74161:sub|:7' = '|74161:44|p74161:sub|QC'
-- Equation name is '_LC060', type is buried
_LC060 = TFFE( _EQ036, GLOBAL( C1024Hz), !_EQ037, VCC, VCC);
_EQ036 = _LC050 & _LC061;
_EQ037 = _X004 & _X005;
_X004 = EXP(!_LC054 & !STAR_STOP);
_X005 = EXP( _LC054 & STAR_STOP);
-- Node name is '|74161:44|p74161:sub|:6' = '|74161:44|p74161:sub|QD'
-- Equation name is '_LC055', type is buried
_LC055 = TFFE( _EQ038, GLOBAL( C1024Hz), !_EQ039, VCC, VCC);
_EQ038 = _LC050 & _LC060 & _LC061;
_EQ039 = _X004 & _X005;
_X004 = EXP(!_LC054 & !STAR_STOP);
_X005 = EXP( _LC054 & STAR_STOP);
-- Node name is ':38'
-- Equation name is '_LC062', type is buried
_LC062 = DFFE( _LC058 $ GND, GLOBAL( C1024Hz), VCC, VCC, VCC);
-- Node name is ':39'
-- Equation name is '_LC058', type is buried
_LC058 = DFFE( _LC054 $ GND, GLOBAL( C1024Hz), VCC, VCC, VCC);
-- Node name is ':40'
-- Equation name is '_LC054', type is buried
_LC054 = DFFE(!STAR_STOP $ GND, _EQ040, VCC, VCC, VCC);
_EQ040 = _LC050 & _LC055 & _LC060 & _LC061;
-- Node name is ':43'
-- Equation name is '_LC056', type is buried
_LC056 = TFFE( VCC, _LC059, VCC, VCC, VCC);
-- Node name is ':55'
-- Equation name is '_LC059', type is buried
_LC059 = DFFE( _LC062 $ GND, GLOBAL( C1024Hz), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, B, C, D
-- _X002 occurs in LABs A, B, C, D
-- _X003 occurs in LABs A, B, C, D
Project Information d:\gongzuo\digital clock\clock_s.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,392K
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