📄 clock_s.rpt
字号:
- 59 D DFFE + t 0 0 0 0 1 0 1 :55
- 55 D TFFE + t 2 2 0 1 4 0 1 |74161:44|p74161:sub|QD (|74161:44|p74161:sub|:6)
- 60 D TFFE + t 2 2 0 1 3 0 2 |74161:44|p74161:sub|QC (|74161:44|p74161:sub|:7)
- 61 D TFFE + t 2 2 0 1 2 0 3 |74161:44|p74161:sub|QB (|74161:44|p74161:sub|:8)
- 50 D TFFE + t 2 2 0 1 1 0 4 |74161:44|p74161:sub|QA (|74161:44|p74161:sub|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\gongzuo\digital clock\clock_s.rpt
clock_s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------- LC16 H0
| +----- LC4 M101
| | +--- LC11 M102
| | | +- LC14 S0
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'A'
LC | | | | | A B C D | Logic cells that feed LAB 'A':
LC4 -> - * * - | * - - - | <-- M101
LC11 -> * * - - | * - - - | <-- M102
Pin
43 -> - - - * | * - - - | <-- C1024Hz
12 -> * * * * | * * * * | <-- SEL_S_CLOCK
LC36 -> - * * - | * - - - | <-- M100
LC58 -> * * * * | * * * * | <-- :39
LC54 -> * * * * | * * * * | <-- :40
LC56 -> * * * * | * * * * | <-- :43
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\clock_s.rpt
clock_s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC19 M1
| +----------- LC20 M2
| | +--------- LC17 M3
| | | +------- LC21 S1
| | | | +----- LC30 S2
| | | | | +--- LC25 S3
| | | | | | +- LC24 S100
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC19 -> * * * - - - - | - * - - | <-- M1
LC20 -> - * * - - - - | - * - - | <-- M2
LC17 -> * - - - - - - | - * * - | <-- M3
LC21 -> - - - * * * - | - * - - | <-- S1
LC30 -> - - - - * * - | - * - - | <-- S2
LC25 -> - - - * - - * | - * - - | <-- S3
Pin
43 -> - - - - - - - | * - - - | <-- C1024Hz
12 -> * * * * * * * | * * * * | <-- SEL_S_CLOCK
LC35 -> * * * - - - - | - * - - | <-- M0
LC14 -> - - - * * * - | - * - - | <-- S0
LC58 -> * * * * * * * | * * * * | <-- :39
LC54 -> * * * * * * * | * * * * | <-- :40
LC56 -> * * * * * * * | * * * * | <-- :43
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\clock_s.rpt
clock_s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------- LC40 H101
| +----------- LC37 H102
| | +--------- LC35 M0
| | | +------- LC36 M100
| | | | +----- LC33 S101
| | | | | +--- LC41 S102
| | | | | | +- LC46 S103
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'C'
LC | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC40 -> * * - - - - - | - - * - | <-- H101
LC37 -> * - - - - - - | - - * - | <-- H102
LC33 -> - - - - * * * | - - * - | <-- S101
LC41 -> - - - - - * * | - - * - | <-- S102
LC46 -> - - * - * - - | - - * - | <-- S103
Pin
43 -> - - - - - - - | * - - - | <-- C1024Hz
12 -> * * * * * * * | * * * * | <-- SEL_S_CLOCK
LC49 -> * * - - - - - | - - * - | <-- H100
LC17 -> - - - * - - - | - * * - | <-- M3
LC24 -> - - - - * * * | - - * - | <-- S100
LC58 -> * * * * * * * | * * * * | <-- :39
LC54 -> * * * * * * * | * * * * | <-- :40
LC56 -> * * * * * * * | * * * * | <-- :43
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\clock_s.rpt
clock_s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC53 H1
| +--------------------------- LC52 H2
| | +------------------------- LC51 H3
| | | +----------------------- LC49 H100
| | | | +--------------------- LC57 H103
| | | | | +------------------- LC64 M103
| | | | | | +----------------- LC62 :38
| | | | | | | +--------------- LC58 :39
| | | | | | | | +------------- LC54 :40
| | | | | | | | | +----------- LC56 :43
| | | | | | | | | | +--------- LC59 :55
| | | | | | | | | | | +------- LC55 |74161:44|p74161:sub|QD
| | | | | | | | | | | | +----- LC60 |74161:44|p74161:sub|QC
| | | | | | | | | | | | | +--- LC61 |74161:44|p74161:sub|QB
| | | | | | | | | | | | | | +- LC50 |74161:44|p74161:sub|QA
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC53 -> * * * - - - - - - - - - - - - | - - - * | <-- H1
LC52 -> - * * - - - - - - - - - - - - | - - - * | <-- H2
LC51 -> * - - * - - - - - - - - - - - | - - - * | <-- H3
LC62 -> - - - - - - - - - - * - - - - | - - - * | <-- :38
LC58 -> * * * * - - * - - - - - - - - | * * * * | <-- :39
LC54 -> * * * * - - - * - - - * * * * | * * * * | <-- :40
LC56 -> * * * * - - - - - * - - - - - | * * * * | <-- :43
LC59 -> - - - - - - - - - * - - - - - | - - - * | <-- :55
LC55 -> - - - - - - - - * - - * - - - | - - - * | <-- |74161:44|p74161:sub|QD
LC60 -> - - - - - - - - * - - * * - - | - - - * | <-- |74161:44|p74161:sub|QC
LC61 -> - - - - - - - - * - - * * * - | - - - * | <-- |74161:44|p74161:sub|QB
LC50 -> - - - - - - - - * - - * * * * | - - - * | <-- |74161:44|p74161:sub|QA
Pin
43 -> - - - - - - - - - - - - - - - | * - - - | <-- C1024Hz
12 -> * * * * - - - - - - - - - - - | * * * * | <-- SEL_S_CLOCK
11 -> - - - - - - - - * - - * * * * | - - - * | <-- STAR_STOP
LC16 -> * * * - - - - - - - - - - - - | - - - * | <-- H0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\clock_s.rpt
clock_s
** EQUATIONS **
C1024Hz : INPUT;
SEL_S_CLOCK : INPUT;
STAR_STOP : INPUT;
-- Node name is 'H0' = '|7490:31|QA'
-- Equation name is 'H0', type is output
H0 = TFFE( VCC, !M102, !_EQ001, VCC, VCC);
_EQ001 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H1' = '|7490:31|QB'
-- Equation name is 'H1', type is output
H1 = DFFE( _EQ002 $ GND, !H0, !_EQ003, VCC, VCC);
_EQ002 = !H1 & !H3;
_EQ003 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H2' = '|7490:31|QC'
-- Equation name is 'H2', type is output
H2 = TFFE( H1, !H0, !_EQ004, VCC, VCC);
_EQ004 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H3' = '|7490:31|QD'
-- Equation name is 'H3', type is output
H3 = DFFE( _EQ005 $ GND, !H0, !_EQ006, VCC, VCC);
_EQ005 = H1 & H2;
_EQ006 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H100' = '|7492:34|QA'
-- Equation name is 'H100', type is output
H100 = TFFE( VCC, !H3, !_EQ007, VCC, VCC);
_EQ007 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H101' = '|7492:34|QB'
-- Equation name is 'H101', type is output
H101 = DFFE( _EQ008 $ GND, !H100, !_EQ009, VCC, VCC);
_EQ008 = !H101 & !H102;
_EQ009 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H102' = '|7492:34|QC'
-- Equation name is 'H102', type is output
H102 = DFFE( H101 $ GND, !H100, !_EQ010, VCC, VCC);
_EQ010 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'H103'
-- Equation name is 'H103', location is LC057, type is output.
H103 = LCELL( GND $ GND);
-- Node name is 'M0' = '|7490:29|QA'
-- Equation name is 'M0', type is output
M0 = TFFE( VCC, !S103, !_EQ011, VCC, VCC);
_EQ011 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
-- Node name is 'M1' = '|7490:29|QB'
-- Equation name is 'M1', type is output
M1 = DFFE( _EQ012 $ GND, !M0, !_EQ013, VCC, VCC);
_EQ012 = !M1 & !M3;
_EQ013 = _X001 & _X002 & _X003;
_X001 = EXP( _LC058 & SEL_S_CLOCK);
_X002 = EXP( _LC056 & SEL_S_CLOCK);
_X003 = EXP(!_LC054 & SEL_S_CLOCK);
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