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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "clk.v"Module <clk> compiledNo errors in compilationAnalysis of file <"clk.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <clk>.WARNING:Xst:916 - "clk.v" line 30: Delay is ignored for synthesis.Module <clk> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clk>. Related source file is "clk.v".WARNING:Xst:647 - Input <reset> is never used.WARNING:Xst:2110 - Clock of register <clk_out> seems to be also used in the data or control logic of that element. Found 1-bit register for signal <clk_out>. Summary: inferred 1 D-type flip-flop(s).Unit <clk> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 1-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clk> ...Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clk, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-5 Number of Slices: 1 out of 1200 0% Number of Slice Flip Flops: 1 out of 2400 0% Number of bonded IOBs: 3 out of 170 1% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_in | BUFGP | 1 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: 2.838ns Maximum output required time after clock: 7.511ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Compiling verilog file "clk.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
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