clk.v

just division the clock into 2

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:54:27 10/08/08
// Design Name:    
// Module Name:    clk
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module clk(clk_in, reset,clk_out);
    input clk_in,reset;
    output clk_out;
	 reg clk_out;
	 always @ (posedge clk_in or negedge clk_in)
	 begin
	 		if(!reset)clk_out=0;
			else
			clk_out=~clk_out;
			#25;clk_out=~clk_out;
	 end


endmodule