clk.gfl

just division the clock into 2

# XST (Creating Lso File) : 
clk.lso
# xst flow : RunXST
clk_summary.html
# xst flow : RunXST
clk.syr
clk.prj
clk.sprj
clk.ana
clk.stx
clk.cmd_log
clk.ngc
clk.ngr
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral VHDL Model
clk_test_v.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_test_v.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_test_v.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_test_v.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf