clk_test_v.fdo

just division the clock into 2

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Oct 08 15:10:33 涓?鍥芥爣鍑嗘椂闂? 2008
##
vlib work
vlog  clk.v
vlog  clk_test.v
vlog  "C:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work clk_test_v glbl
do {clk_test_v.udo}
view wave
add wave *
view structure
view signals
run 1000ns