clk_test.v

来自「just division the clock into 2」· Verilog 代码 · 共 58 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:02:53 10/08/2008
// Design Name:   clk
// Module Name:   clk_test.v
// Project Name:  clk
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: clk
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module clk_test_v;

	// Inputs
	reg clk_in;
	reg reset;

	// Outputs
	wire clk_out;
	always #50 clk_in = ~clk_in;
	// Instantiate the Unit Under Test (UUT)
	clk uut (
		.clk_in(clk_in), 
		.reset(reset), 
		.clk_out(clk_out)
	);

	initial begin
		// Initialize Inputs
		clk_in = 0;
		reset = 1;

		// Wait 100 ns for global reset to finish
		#100;
      #100 reset = 0;
		#100 reset = 0;
		#10000 $stop;
  
		// Add stimulus here

	end
      
endmodule