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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "blocking.v"ERROR:HDLCompilers:120 - "blocking.v" line 27 Illegal redeclaration of input 'c' as a regModule <blocking> compiledAnalysis of file <"blocking.prj"> failed.--> Total memory usage is 76244 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "blocking.v"ERROR:HDLCompilers:120 - "blocking.v" line 28 Illegal redeclaration of input 'c' as a regModule <blocking> compiledAnalysis of file <"blocking.prj"> failed.--> Total memory usage is 76244 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "blocking.v"Module <blocking> compiledNo errors in compilationAnalysis of file <"blocking.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <blocking>.Module <blocking> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <blocking>. Related source file is "blocking.v". Register <c> equivalent to <b> has been removed Found 4-bit register for signal <b>. Summary: inferred 4 D-type flip-flop(s).Unit <blocking> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 4-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <blocking> ...Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block blocking, actual ratio is 0.FlipFlop b_3 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop b_2 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop b_1 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop b_0 has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-5 Number of Slices: 5 out of 1200 0% Number of Slice Flip Flops: 8 out of 2400 0% Number of bonded IOBs: 13 out of 170 7% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 8 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: 2.866ns Maximum output required time after clock: 7.511ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Compiling verilog file "blocking.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "non_blocking.v"Module <non_blocking> compiledNo errors in compilationAnalysis of file <"non_blocking.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <non_blocking>.Module <non_blocking> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <non_blocking>. Related source file is "non_blocking.v". Found 4-bit register for signal <b>. Found 4-bit register for signal <c>. Summary: inferred 8 D-type flip-flop(s).Unit <non_blocking> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 2 4-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <non_blocking> ...Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block non_blocking, actual ratio is 0.FlipFlop b_3 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop b_2 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop b_1 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop b_0 has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-5 Number of Slices: 7 out of 1200 0% Number of Slice Flip Flops: 12 out of 2400 0% Number of bonded IOBs: 13 out of 170 7% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 12 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 3.009ns (Maximum Frequency: 332.336MHz) Minimum input arrival time before clock: 2.866ns Maximum output required time after clock: 7.511ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Compiling verilog file "blocking.v"tdtfi(verilog) completed successfully.
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