blocking_test.v

来自「blocking fuzhi and non_blocking」· Verilog 代码 · 共 57 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:49:06 10/08/2008
// Design Name:   blocking
// Module Name:   blocking_test.v
// Project Name:  blocking
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: blocking
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module blocking_test_v;

	// Inputs
	reg [3:0] a;
	reg clk;

	// Outputs
	wire [3:0] b;
	wire [3:0] c;

	// Instantiate the Unit Under Test (UUT)
	blocking uut (
		.a(a), 
		.clk(clk), 
		.b(b), 
		.c(c)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule