compare_top.v

blocking fuzhi and non_blocking

`timescale 1ns / 1ps
`include "./blocking.v"
`include "./non_blocking.v"

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:52:55 10/08/2008
// Design Name:   blocking
// Module Name:   compare_Top.v
// Project Name:  blocking
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: blocking
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module compare_Top_v;

	// Inputs
	wire [3:0] b1,c1,b2,c2;
   reg [3:0] a;
	reg clk;


	// Instantiate the Unit Under Test (UUT)
	initial
	begin
		clk = 0;
	forever #50 clk = ~clk;
	end

	initial
	begin
		a = 4'h3;
		$display("____________________________");
		# 100 a = 4'h7;
		$display("____________________________");
		# 100 a = 4'hf;
		$display("____________________________");
		# 100 a = 4'ha;
		$display("____________________________");
		# 100 a = 4'h2;
		$display("____________________________");
		# 100 $display("____________________________");
		$stop;
		end

		non_blocking non_blocking(clk,a,b2,c2);
		blocking blocking(clk,a,b1,c1);
endmodule