📄 prev_cmp_biaojue.qmsg
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Allocated 194 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 19:56:28 2007 " "Info: Processing ended: Mon Jun 25 19:56:28 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 25 19:56:29 2007 " "Info: Processing started: Mon Jun 25 19:56:29 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off BIAOJUE -c BIAOJUE --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BIAOJUE -c BIAOJUE --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } { "d:/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register QALL\[1\]~reg0 register QQ~reg0 310.46 MHz 3.221 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 310.46 MHz between source register \"QALL\[1\]~reg0\" and destination register \"QQ~reg0\" (period= 3.221 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.007 ns + Longest register register " "Info: + Longest register to register delay is 3.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns QALL\[1\]~reg0 1 REG LCFF_X41_Y35_N31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X41_Y35_N31; Fanout = 5; REG Node = 'QALL\[1\]~reg0'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { QALL[1]~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.150 ns) 0.468 ns Add0~96 2 COMB LCCOMB_X41_Y35_N0 2 " "Info: 2: + IC(0.318 ns) + CELL(0.150 ns) = 0.468 ns; Loc. = LCCOMB_X41_Y35_N0; Fanout = 2; COMB Node = 'Add0~96'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { QALL[1]~reg0 Add0~96 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.420 ns) 1.131 ns Add4~196 3 COMB LCCOMB_X41_Y35_N4 1 " "Info: 3: + IC(0.243 ns) + CELL(0.420 ns) = 1.131 ns; Loc. = LCCOMB_X41_Y35_N4; Fanout = 1; COMB Node = 'Add4~196'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.663 ns" { Add0~96 Add4~196 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.419 ns) 1.800 ns Add4~201 4 COMB LCCOMB_X41_Y35_N30 2 " "Info: 4: + IC(0.250 ns) + CELL(0.419 ns) = 1.800 ns; Loc. = LCCOMB_X41_Y35_N30; Fanout = 2; COMB Node = 'Add4~201'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.669 ns" { Add4~196 Add4~201 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.419 ns) 2.923 ns LessThan0~116 5 COMB LCCOMB_X41_Y35_N28 1 " "Info: 5: + IC(0.704 ns) + CELL(0.419 ns) = 2.923 ns; Loc. = LCCOMB_X41_Y35_N28; Fanout = 1; COMB Node = 'LessThan0~116'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { Add4~201 LessThan0~116 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1731 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.007 ns QQ~reg0 6 REG LCFF_X41_Y35_N29 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.007 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.492 ns ( 49.62 % ) " "Info: Total cell delay = 1.492 ns ( 49.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.515 ns ( 50.38 % ) " "Info: Total interconnect delay = 1.515 ns ( 50.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.007 ns" { QALL[1]~reg0 Add0~96 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "3.007 ns" { QALL[1]~reg0 Add0~96 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } { 0.000ns 0.318ns 0.243ns 0.250ns 0.704ns 0.000ns } { 0.000ns 0.150ns 0.420ns 0.419ns 0.419ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.683 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns QQ~reg0 3 REG LCFF_X41_Y35_N29 1 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QQ~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.683 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns QALL\[1\]~reg0 3 REG LCFF_X41_Y35_N31 5 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N31; Fanout = 5; REG Node = 'QALL\[1\]~reg0'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { CLK~clkctrl QALL[1]~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QALL[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QALL[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QQ~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QALL[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QALL[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.007 ns" { QALL[1]~reg0 Add0~96 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "3.007 ns" { QALL[1]~reg0 Add0~96 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } { 0.000ns 0.318ns 0.243ns 0.250ns 0.704ns 0.000ns } { 0.000ns 0.150ns 0.420ns 0.419ns 0.419ns 0.084ns } "" } } { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QQ~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QALL[1]~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QALL[1]~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "QQ~reg0 FF\[3\] CLK 6.370 ns register " "Info: tsu for register \"QQ~reg0\" (data pin = \"FF\[3\]\", clock pin = \"CLK\") is 6.370 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.089 ns + Longest pin register " "Info: + Longest pin to register delay is 9.089 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns FF\[3\] 1 PIN PIN_B15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B15; Fanout = 3; PIN Node = 'FF\[3\]'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { FF[3] } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.081 ns) + CELL(0.438 ns) 6.369 ns Add2~177 2 COMB LCCOMB_X40_Y35_N14 2 " "Info: 2: + IC(5.081 ns) + CELL(0.438 ns) = 6.369 ns; Loc. = LCCOMB_X40_Y35_N14; Fanout = 2; COMB Node = 'Add2~177'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "5.519 ns" { FF[3] Add2~177 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.437 ns) 7.213 ns Add4~196 3 COMB LCCOMB_X41_Y35_N4 1 " "Info: 3: + IC(0.407 ns) + CELL(0.437 ns) = 7.213 ns; Loc. = LCCOMB_X41_Y35_N4; Fanout = 1; COMB Node = 'Add4~196'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.844 ns" { Add2~177 Add4~196 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.419 ns) 7.882 ns Add4~201 4 COMB LCCOMB_X41_Y35_N30 2 " "Info: 4: + IC(0.250 ns) + CELL(0.419 ns) = 7.882 ns; Loc. = LCCOMB_X41_Y35_N30; Fanout = 2; COMB Node = 'Add4~201'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.669 ns" { Add4~196 Add4~201 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.419 ns) 9.005 ns LessThan0~116 5 COMB LCCOMB_X41_Y35_N28 1 " "Info: 5: + IC(0.704 ns) + CELL(0.419 ns) = 9.005 ns; Loc. = LCCOMB_X41_Y35_N28; Fanout = 1; COMB Node = 'LessThan0~116'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { Add4~201 LessThan0~116 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1731 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.089 ns QQ~reg0 6 REG LCFF_X41_Y35_N29 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.089 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.647 ns ( 29.12 % ) " "Info: Total cell delay = 2.647 ns ( 29.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.442 ns ( 70.88 % ) " "Info: Total interconnect delay = 6.442 ns ( 70.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "9.089 ns" { FF[3] Add2~177 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "9.089 ns" { FF[3] FF[3]~combout Add2~177 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } { 0.000ns 0.000ns 5.081ns 0.407ns 0.250ns 0.704ns 0.000ns } { 0.000ns 0.850ns 0.438ns 0.437ns 0.419ns 0.419ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.683 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns QQ~reg0 3 REG LCFF_X41_Y35_N29 1 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QQ~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "9.089 ns" { FF[3] Add2~177 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "9.089 ns" { FF[3] FF[3]~combout Add2~177 Add4~196 Add4~201 LessThan0~116 QQ~reg0 } { 0.000ns 0.000ns 5.081ns 0.407ns 0.250ns 0.704ns 0.000ns } { 0.000ns 0.850ns 0.438ns 0.437ns 0.419ns 0.419ns 0.084ns } "" } } { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { CLK CLK~clkctrl QQ~reg0 } "NODE_NAME" } } { "d:/alter/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { CLK CLK~combout CLK~clkctrl QQ~reg0 } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK QALL\[1\] QALL\[1\]~reg0 8.077 ns register " "Info: tco from clock \"CLK\" to destination pin \"QALL\[1\]\" through register \"QALL\[1\]~reg0\" is 8.077 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.683 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 1⌨️ 快捷键说明
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