prev_cmp_biaojue.fit.qmsg

这是一个用VHDL语言实现的非常实用的表决器

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.128 ns register register " "Info: Estimated most critical path is register to register delay of 3.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns QALL\[1\]~reg0 1 REG LAB_X41_Y35 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X41_Y35; Fanout = 5; REG Node = 'QALL\[1\]~reg0'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { QALL[1]~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.275 ns) 0.623 ns Add0~96 2 COMB LAB_X41_Y35 2 " "Info: 2: + IC(0.348 ns) + CELL(0.275 ns) = 0.623 ns; Loc. = LAB_X41_Y35; Fanout = 2; COMB Node = 'Add0~96'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.623 ns" { QALL[1]~reg0 Add0~96 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.414 ns) 1.434 ns Add4~197 3 COMB LAB_X41_Y35 2 " "Info: 3: + IC(0.397 ns) + CELL(0.414 ns) = 1.434 ns; Loc. = LAB_X41_Y35; Fanout = 2; COMB Node = 'Add4~197'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Add0~96 Add4~197 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.505 ns Add4~199 4 COMB LAB_X41_Y35 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.505 ns; Loc. = LAB_X41_Y35; Fanout = 1; COMB Node = 'Add4~199'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add4~197 Add4~199 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.915 ns Add4~202 5 COMB LAB_X41_Y35 1 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.915 ns; Loc. = LAB_X41_Y35; Fanout = 1; COMB Node = 'Add4~202'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add4~199 Add4~202 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 2.480 ns Add4~204 6 COMB LAB_X41_Y35 2 " "Info: 6: + IC(0.145 ns) + CELL(0.420 ns) = 2.480 ns; Loc. = LAB_X41_Y35; Fanout = 2; COMB Node = 'Add4~204'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { Add4~202 Add4~204 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 935 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.149 ns) 3.044 ns LessThan0~116 7 COMB LAB_X41_Y35 1 " "Info: 7: + IC(0.415 ns) + CELL(0.149 ns) = 3.044 ns; Loc. = LAB_X41_Y35; Fanout = 1; COMB Node = 'LessThan0~116'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { Add4~204 LessThan0~116 } "NODE_NAME" } } { "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/alter/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1731 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.128 ns QQ~reg0 8 REG LAB_X41_Y35 1 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 3.128 ns; Loc. = LAB_X41_Y35; Fanout = 1; REG Node = 'QQ~reg0'" {  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { LessThan0~116 QQ~reg0 } "NODE_NAME" } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.823 ns ( 58.28 % ) " "Info: Total cell delay = 1.823 ns ( 58.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.305 ns ( 41.72 % ) " "Info: Total interconnect delay = 1.305 ns ( 41.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.128 ns" { QALL[1]~reg0 Add0~96 Add4~197 Add4~199 Add4~202 Add4~204 LessThan0~116 QQ~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X33_Y24 X43_Y36 " "Info: The peak interconnect region extends from location X33_Y24 to location X43_Y36" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "QQ 0 " "Info: Pin \"QQ\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "QALL\[1\] 0 " "Info: Pin \"QALL\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "QALL\[2\] 0 " "Info: Pin \"QALL\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "QALL\[3\] 0 " "Info: Pin \"QALL\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SHIJIAN\[0\] 0 " "Info: Pin \"SHIJIAN\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SHIJIAN\[1\] 0 " "Info: Pin \"SHIJIAN\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SHIJIAN\[2\] 0 " "Info: Pin \"SHIJIAN\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SHIJIAN\[3\] 0 " "Info: Pin \"SHIJIAN\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/altera/表决器/BIAOJUE.fit.smsg " "Info: Generated suppressed messages file F:/altera/表决器/BIAOJUE.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "243 " "Info: Allocated 243 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 19:56:09 2007 " "Info: Processing ended: Mon Jun 25 19:56:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}