biaojue.hier_info

这是一个用VHDL语言实现的非常实用的表决器

|BIAOJUE
FF[5] => Add4.IN6
FF[4] => Add3.IN6
FF[3] => Add2.IN6
FF[2] => Add1.IN6
FF[1] => Add0.IN3
QQ <= QQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
QALL[1] <= QALL[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
QALL[2] <= QALL[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
QALL[3] <= QALL[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SHIJIAN[0] <= SHIJIAN[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SHIJIAN[1] <= SHIJIAN[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SHIJIAN[2] <= SHIJIAN[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SHIJIAN[3] <= SHIJIAN[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FUWEI => SUO.ACLR
FUWEI => SUM[1].ACLR
FUWEI => SUM[2].ACLR
FUWEI => SUM[3].ACLR
FUWEI => QQ~reg0.ACLR
FUWEI => SHIJIAN[3]~reg0.PRESET
FUWEI => SHIJIAN[2]~reg0.ACLR
FUWEI => SHIJIAN[1]~reg0.PRESET
FUWEI => SHIJIAN[0]~reg0.ACLR
FUWEI => QALL[3]~reg0.ACLR
FUWEI => QALL[2]~reg0.ACLR
FUWEI => QALL[1]~reg0.ACLR
KAISHI => QALL[1]~reg0.ENA
KAISHI => SUO.ENA
KAISHI => SUM[1].ENA
KAISHI => SUM[2].ENA
KAISHI => SUM[3].ENA
KAISHI => QQ~reg0.ENA
KAISHI => SHIJIAN[3]~reg0.ENA
KAISHI => SHIJIAN[2]~reg0.ENA
KAISHI => SHIJIAN[1]~reg0.ENA
KAISHI => SHIJIAN[0]~reg0.ENA
KAISHI => QALL[3]~reg0.ENA
KAISHI => QALL[2]~reg0.ENA
CLK => SUO.CLK
CLK => SUM[1].CLK
CLK => SUM[2].CLK
CLK => SUM[3].CLK
CLK => QQ~reg0.CLK
CLK => SHIJIAN[3]~reg0.CLK
CLK => SHIJIAN[2]~reg0.CLK
CLK => SHIJIAN[1]~reg0.CLK
CLK => SHIJIAN[0]~reg0.CLK
CLK => QALL[3]~reg0.CLK
CLK => QALL[2]~reg0.CLK
CLK => QALL[1]~reg0.CLK