prev_cmp_biaojue.map.qmsg

这是一个用VHDL语言实现的非常实用的表决器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 25 19:55:50 2007 " "Info: Processing started: Mon Jun 25 19:55:50 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BIAOJUE -c BIAOJUE " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BIAOJUE -c BIAOJUE" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BIAOJUE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BIAOJUE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BIAOJUE-FUNG " "Info: Found design unit 1: BIAOJUE-FUNG" {  } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 BIAOJUE " "Info: Found entity 1: BIAOJUE" {  } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "BIAOJUE " "Info: Elaborating entity \"BIAOJUE\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "SUM\[3\] QALL\[1\]~reg0 " "Info: Duplicate register \"SUM\[3\]\" merged to single register \"QALL\[1\]~reg0\"" {  } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "QALL\[3\]~reg0 SUM\[1\] " "Info: Duplicate register \"QALL\[3\]~reg0\" merged to single register \"SUM\[1\]\"" {  } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "QALL\[2\]~reg0 SUM\[2\] " "Info: Duplicate register \"QALL\[2\]~reg0\" merged to single register \"SUM\[2\]\"" {  } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 -1 0 } } { "BIAOJUE.vhd" "" { Text "F:/altera/表决器/BIAOJUE.vhd" 18 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Info: Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "24 " "Info: Implemented 24 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "158 " "Info: Allocated 158 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 19:55:53 2007 " "Info: Processing ended: Mon Jun 25 19:55:53 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}