biaojue.map.rpt

这是一个用VHDL语言实现的非常实用的表决器

+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; BIAOJUE.vhd                      ; yes             ; User VHDL File  ; F:/altera/表决器/BIAOJUE.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 21    ;
;                                             ;       ;
; Total combinational functions               ; 21    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 11    ;
;     -- 3 input functions                    ; 8     ;
;     -- <=2 input functions                  ; 2     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 19    ;
;     -- arithmetic mode                      ; 2     ;
;                                             ;       ;
; Total registers                             ; 9     ;
;     -- Dedicated logic registers            ; 9     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 16    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 9     ;
; Total fan-out                               ; 111   ;
; Average fan-out                             ; 2.41  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |BIAOJUE                   ; 21 (21)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 16   ; 0            ; |BIAOJUE            ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------+
; Registers Removed During Synthesis                               ;
+---------------------------------------+--------------------------+
; Register name                         ; Reason for Removal       ;
+---------------------------------------+--------------------------+
; SUM[3]                                ; Merged with QALL[1]~reg0 ;
; QALL[3]~reg0                          ; Merged with SUM[1]       ;
; QALL[2]~reg0                          ; Merged with SUM[2]       ;
; Total Number of Removed Registers = 3 ;                          ;
+---------------------------------------+--------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 9     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; SHIJIAN[1]~reg0                        ; 5       ;
; SHIJIAN[3]~reg0                        ; 3       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |BIAOJUE|SUM~3             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Jun 25 19:55:50 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BIAOJUE -c BIAOJUE
Info: Found 2 design units, including 1 entities, in source file BIAOJUE.vhd
    Info: Found design unit 1: BIAOJUE-FUNG
    Info: Found entity 1: BIAOJUE
Info: Elaborating entity "BIAOJUE" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info: Duplicate register "SUM[3]" merged to single register "QALL[1]~reg0"
    Info: Duplicate register "QALL[3]~reg0" merged to single register "SUM[1]"
    Info: Duplicate register "QALL[2]~reg0" merged to single register "SUM[2]"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 40 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 8 output pins
    Info: Implemented 24 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 158 megabytes of memory during processing
    Info: Processing ended: Mon Jun 25 19:55:53 2007
    Info: Elapsed time: 00:00:03