biaojue.tan.rpt

这是一个用VHDL语言实现的非常实用的表决器

; N/A           ; None        ; -3.378 ns ; KAISHI ; SUM[2]          ; CLK      ;
; N/A           ; None        ; -3.378 ns ; KAISHI ; SUM[1]          ; CLK      ;
; N/A           ; None        ; -3.378 ns ; KAISHI ; QQ~reg0         ; CLK      ;
; N/A           ; None        ; -3.790 ns ; KAISHI ; SHIJIAN[1]~reg0 ; CLK      ;
; N/A           ; None        ; -3.791 ns ; KAISHI ; SHIJIAN[2]~reg0 ; CLK      ;
; N/A           ; None        ; -4.349 ns ; FF[2]  ; SUM[2]          ; CLK      ;
; N/A           ; None        ; -4.489 ns ; FF[2]  ; SUM[1]          ; CLK      ;
; N/A           ; None        ; -4.502 ns ; FF[5]  ; SUM[2]          ; CLK      ;
; N/A           ; None        ; -4.574 ns ; FF[2]  ; QALL[1]~reg0    ; CLK      ;
; N/A           ; None        ; -4.621 ns ; FF[5]  ; SUM[1]          ; CLK      ;
; N/A           ; None        ; -4.728 ns ; FF[5]  ; QALL[1]~reg0    ; CLK      ;
; N/A           ; None        ; -4.791 ns ; FF[3]  ; SUM[2]          ; CLK      ;
; N/A           ; None        ; -4.876 ns ; FF[2]  ; QQ~reg0         ; CLK      ;
; N/A           ; None        ; -4.907 ns ; FF[3]  ; SUM[1]          ; CLK      ;
; N/A           ; None        ; -5.017 ns ; FF[3]  ; QALL[1]~reg0    ; CLK      ;
; N/A           ; None        ; -5.029 ns ; FF[5]  ; QQ~reg0         ; CLK      ;
; N/A           ; None        ; -5.315 ns ; FF[3]  ; QQ~reg0         ; CLK      ;
+---------------+-------------+-----------+--------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Jun 25 19:56:29 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BIAOJUE -c BIAOJUE --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 310.46 MHz between source register "QALL[1]~reg0" and destination register "QQ~reg0" (period= 3.221 ns)
    Info: + Longest register to register delay is 3.007 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X41_Y35_N31; Fanout = 5; REG Node = 'QALL[1]~reg0'
        Info: 2: + IC(0.318 ns) + CELL(0.150 ns) = 0.468 ns; Loc. = LCCOMB_X41_Y35_N0; Fanout = 2; COMB Node = 'Add0~96'
        Info: 3: + IC(0.243 ns) + CELL(0.420 ns) = 1.131 ns; Loc. = LCCOMB_X41_Y35_N4; Fanout = 1; COMB Node = 'Add4~196'
        Info: 4: + IC(0.250 ns) + CELL(0.419 ns) = 1.800 ns; Loc. = LCCOMB_X41_Y35_N30; Fanout = 2; COMB Node = 'Add4~201'
        Info: 5: + IC(0.704 ns) + CELL(0.419 ns) = 2.923 ns; Loc. = LCCOMB_X41_Y35_N28; Fanout = 1; COMB Node = 'LessThan0~116'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.007 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'
        Info: Total cell delay = 1.492 ns ( 49.62 % )
        Info: Total interconnect delay = 1.515 ns ( 50.38 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.683 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'
            Info: Total cell delay = 1.536 ns ( 57.25 % )
            Info: Total interconnect delay = 1.147 ns ( 42.75 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.683 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N31; Fanout = 5; REG Node = 'QALL[1]~reg0'
            Info: Total cell delay = 1.536 ns ( 57.25 % )
            Info: Total interconnect delay = 1.147 ns ( 42.75 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "QQ~reg0" (data pin = "FF[3]", clock pin = "CLK") is 6.370 ns
    Info: + Longest pin to register delay is 9.089 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B15; Fanout = 3; PIN Node = 'FF[3]'
        Info: 2: + IC(5.081 ns) + CELL(0.438 ns) = 6.369 ns; Loc. = LCCOMB_X40_Y35_N14; Fanout = 2; COMB Node = 'Add2~177'
        Info: 3: + IC(0.407 ns) + CELL(0.437 ns) = 7.213 ns; Loc. = LCCOMB_X41_Y35_N4; Fanout = 1; COMB Node = 'Add4~196'
        Info: 4: + IC(0.250 ns) + CELL(0.419 ns) = 7.882 ns; Loc. = LCCOMB_X41_Y35_N30; Fanout = 2; COMB Node = 'Add4~201'
        Info: 5: + IC(0.704 ns) + CELL(0.419 ns) = 9.005 ns; Loc. = LCCOMB_X41_Y35_N28; Fanout = 1; COMB Node = 'LessThan0~116'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.089 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'
        Info: Total cell delay = 2.647 ns ( 29.12 % )
        Info: Total interconnect delay = 6.442 ns ( 70.88 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.683 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N29; Fanout = 1; REG Node = 'QQ~reg0'
        Info: Total cell delay = 1.536 ns ( 57.25 % )
        Info: Total interconnect delay = 1.147 ns ( 42.75 % )
Info: tco from clock "CLK" to destination pin "QALL[1]" through register "QALL[1]~reg0" is 8.077 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.683 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N31; Fanout = 5; REG Node = 'QALL[1]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.25 % )
        Info: Total interconnect delay = 1.147 ns ( 42.75 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.144 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X41_Y35_N31; Fanout = 5; REG Node = 'QALL[1]~reg0'
        Info: 2: + IC(2.365 ns) + CELL(2.779 ns) = 5.144 ns; Loc. = PIN_F21; Fanout = 0; PIN Node = 'QALL[1]'
        Info: Total cell delay = 2.779 ns ( 54.02 % )
        Info: Total interconnect delay = 2.365 ns ( 45.98 % )
Info: th for register "SUM[2]" (data pin = "FF[4]", clock pin = "CLK") is -0.810 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.683 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X41_Y35_N17; Fanout = 4; REG Node = 'SUM[2]'
        Info: Total cell delay = 1.536 ns ( 57.25 % )
        Info: Total interconnect delay = 1.147 ns ( 42.75 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.759 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 3; PIN Node = 'FF[4]'
        Info: 2: + IC(1.259 ns) + CELL(0.150 ns) = 2.388 ns; Loc. = LCCOMB_X40_Y35_N30; Fanout = 2; COMB Node = 'Add2~176'
        Info: 3: + IC(0.437 ns) + CELL(0.438 ns) = 3.263 ns; Loc. = LCCOMB_X41_Y35_N6; Fanout = 1; COMB Node = 'Add4~198'
        Info: 4: + IC(0.262 ns) + CELL(0.150 ns) = 3.675 ns; Loc. = LCCOMB_X41_Y35_N16; Fanout = 2; COMB Node = 'Add4~200'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 3.759 ns; Loc. = LCFF_X41_Y35_N17; Fanout = 4; REG Node = 'SUM[2]'
        Info: Total cell delay = 1.801 ns ( 47.91 % )
        Info: Total interconnect delay = 1.958 ns ( 52.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Mon Jun 25 19:56:30 2007
    Info: Elapsed time: 00:00:01