📄 biaojue.tan.rpt
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Classic Timing Analyzer report for BIAOJUE
Mon Jun 25 19:56:30 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+--------------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------+---------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.370 ns ; FF[3] ; QQ~reg0 ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 8.077 ns ; QALL[1]~reg0 ; QALL[1] ; CLK ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.810 ns ; FF[4] ; SUM[2] ; -- ; CLK ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; 310.46 MHz ( period = 3.221 ns ) ; QALL[1]~reg0 ; QQ~reg0 ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+--------------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 310.46 MHz ( period = 3.221 ns ) ; QALL[1]~reg0 ; QQ~reg0 ; CLK ; CLK ; None ; None ; 3.007 ns ;
; N/A ; 333.33 MHz ( period = 3.000 ns ) ; SUM[2] ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.786 ns ;
; N/A ; 375.09 MHz ( period = 2.666 ns ) ; QALL[1]~reg0 ; SUM[1] ; CLK ; CLK ; None ; None ; 2.452 ns ;
; N/A ; 380.08 MHz ( period = 2.631 ns ) ; SUO ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.417 ns ;
; N/A ; 381.39 MHz ( period = 2.622 ns ) ; SHIJIAN[0]~reg0 ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.408 ns ;
; N/A ; 384.47 MHz ( period = 2.601 ns ) ; SHIJIAN[1]~reg0 ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.386 ns ;
; N/A ; 384.62 MHz ( period = 2.600 ns ) ; SUM[1] ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.386 ns ;
; N/A ; 385.80 MHz ( period = 2.592 ns ) ; SUM[2] ; SUM[1] ; CLK ; CLK ; None ; None ; 2.378 ns ;
; N/A ; 387.45 MHz ( period = 2.581 ns ) ; SHIJIAN[3]~reg0 ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.367 ns ;
; N/A ; 403.71 MHz ( period = 2.477 ns ) ; SHIJIAN[2]~reg0 ; QQ~reg0 ; CLK ; CLK ; None ; None ; 2.262 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; QALL[1]~reg0 ; SUM[2] ; CLK ; CLK ; None ; None ; 2.010 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SUM[1] ; SUM[1] ; CLK ; CLK ; None ; None ; 1.978 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; QALL[1]~reg0 ; QALL[1]~reg0 ; CLK ; CLK ; None ; None ; 1.884 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SHIJIAN[0]~reg0 ; SHIJIAN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SHIJIAN[0]~reg0 ; SHIJIAN[1]~reg0 ; CLK ; CLK ; None ; None ; 1.872 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SHIJIAN[1]~reg0 ; SHIJIAN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.851 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SHIJIAN[1]~reg0 ; SHIJIAN[1]~reg0 ; CLK ; CLK ; None ; None ; 1.850 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SHIJIAN[3]~reg0 ; SHIJIAN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.832 ns ;
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