mux_uab.tdf

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TDF
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=4 LPM_WIDTH=4 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_uab
( 
	data[15..0]	:	input;
	result[3..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[3..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data150w[3..0]	: WIRE;
	w_data180w[3..0]	: WIRE;
	w_data205w[3..0]	: WIRE;
	w_data230w[3..0]	: WIRE;
	w_result151w	: WIRE;
	w_result161w	: WIRE;
	w_result162w	: WIRE;
	w_result181w	: WIRE;
	w_result191w	: WIRE;
	w_result192w	: WIRE;
	w_result206w	: WIRE;
	w_result216w	: WIRE;
	w_result217w	: WIRE;
	w_result231w	: WIRE;
	w_result241w	: WIRE;
	w_result242w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result231w, w_result206w, w_result181w, w_result151w);
	sel_node[] = ( sel[1..0]);
	w_data150w[] = ( data[12..12], data[8..8], data[4..4], data[0..0]);
	w_data180w[] = ( data[13..13], data[9..9], data[5..5], data[1..1]);
	w_data205w[] = ( data[14..14], data[10..10], data[6..6], data[2..2]);
	w_data230w[] = ( data[15..15], data[11..11], data[7..7], data[3..3]);
	w_result151w = w_result161w;
	w_result161w = (((w_data150w[1..1] & sel_node[0..0]) & (! w_result162w)) # (w_result162w & (w_data150w[3..3] # (! sel_node[0..0]))));
	w_result162w = (((w_data150w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data150w[2..2])));
	w_result181w = w_result191w;
	w_result191w = (((w_data180w[1..1] & sel_node[0..0]) & (! w_result192w)) # (w_result192w & (w_data180w[3..3] # (! sel_node[0..0]))));
	w_result192w = (((w_data180w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data180w[2..2])));
	w_result206w = w_result216w;
	w_result216w = (((w_data205w[1..1] & sel_node[0..0]) & (! w_result217w)) # (w_result217w & (w_data205w[3..3] # (! sel_node[0..0]))));
	w_result217w = (((w_data205w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data205w[2..2])));
	w_result231w = w_result241w;
	w_result241w = (((w_data230w[1..1] & sel_node[0..0]) & (! w_result242w)) # (w_result242w & (w_data230w[3..3] # (! sel_node[0..0]))));
	w_result242w = (((w_data230w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data230w[2..2])));
END;
--VALID FILE

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