i2c_altera.map.qmsg

来自「AV视频信号输入后」· QMSG 代码 · 共 136 行 · 第 1/5 页

{ "Warning" "WGDFX_PIN_IGNORED" "PDATA " "Warning: Pin \"PDATA\" not connected" {  } { { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 880 1680 1848 896 "PDATA\[7..0\]" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C I2C:inst1 " "Info: Elaborating entity \"I2C\" for hierarchy \"I2C:inst1\"" {  } { { "I2C_ALTERA.bdf" "inst1" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 1072 1336 1504 1296 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "div_by_n.tdf 1 1 " "Info: Using design file div_by_n.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_n " "Info: Found entity 1: div_by_n" {  } { { "div_by_n.tdf" "" { Text "E:/code/EP2C20/vbuffer1/div_by_n.tdf" 19 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_by_n I2C:inst1\|div_by_n:div_by_x " "Info: Elaborating entity \"div_by_n\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\"" {  } { { "I2C.TDF" "div_by_x" { Text "E:/code/EP2C20/vbuffer1/I2C.TDF" 85 3 0 } }  } 0}
{ "Info" "ITDFX_ASSERTION" "div_by_n module will operate internally using 5 bits. " "Info: Assertion information: div_by_n module will operate internally using 5 bits." {  } { { "div_by_n.tdf" "" { Text "E:/code/EP2C20/vbuffer1/div_by_n.tdf" 39 3 0 } } { "I2C.TDF" "" { Text "E:/code/EP2C20/vbuffer1/I2C.TDF" 85 3 0 } } { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 1072 1336 1504 1296 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter I2C:inst1\|div_by_n:div_by_x\|lpm_counter:counter " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_counter:counter\"" {  } { { "div_by_n.tdf" "counter" { Text "E:/code/EP2C20/vbuffer1/div_by_n.tdf" 29 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rf6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rf6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rf6 " "Info: Found entity 1: cntr_rf6" {  } { { "db/cntr_rf6.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_rf6.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_rf6 I2C:inst1\|div_by_n:div_by_x\|lpm_counter:counter\|cntr_rf6:auto_generated " "Info: Elaborating entity \"cntr_rf6\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_counter:counter\|cntr_rf6:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 251 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 262 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_compare I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002 " "Info: Elaborating entity \"lpm_compare\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\"" {  } { { "div_by_n.tdf" "\$00002" { Text "E:/code/EP2C20/vbuffer1/div_by_n.tdf" 44 13 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/comptree.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/comptree.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 comptree " "Info: Found entity 1: comptree" {  } { { "comptree.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 102 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comptree I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator " "Info: Elaborating entity \"comptree\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\"" {  } { { "lpm_compare.tdf" "comparator" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 295 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpchain " "Info: Found entity 1: cmpchain" {  } { { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 84 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpchain I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end " "Info: Elaborating entity \"cmpchain\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\"" {  } { { "comptree.tdf" "cmp_end" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 171 5 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comptree I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp " "Info: Elaborating entity \"comptree\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\"" {  } { { "cmpchain.tdf" "comp" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 134 7 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpchain I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|cmpchain:cmp\[0\] " "Info: Elaborating entity \"cmpchain\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|cmpchain:cmp\[0\]\"" {  } { { "comptree.tdf" "cmp\[0\]" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 131 7 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpchain I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|cmpchain:cmp_end " "Info: Elaborating entity \"cmpchain\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|cmpchain:cmp_end\"" {  } { { "comptree.tdf" "cmp_end" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 138 5 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comptree I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree " "Info: Elaborating entity \"comptree\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\"" {  } { { "comptree.tdf" "sub_comptree" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 157 4 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpchain I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|cmpchain:cmp_end " "Info: Elaborating entity \"cmpchain\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|cmpchain:cmp_end\"" {  } { { "comptree.tdf" "cmp_end" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 171 5 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|altshift:aeb_ext_lat_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"I2C:inst1\|div_by_n:div_by_x\|lpm_compare:\$00002\|altshift:aeb_ext_lat_ffs\"" {  } { { "lpm_compare.tdf" "aeb_ext_lat_ffs" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 309 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:inst19 " "Info: Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:inst19\"" {  } { { "I2C_ALTERA.bdf" "inst19" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 1504 936 1032 1600 "inst19" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clk_gen.v(19) " "Warning: Verilog HDL assignment warning at clk_gen.v(19): truncated value with size 32 to match size of target (2)" {  } { { "clk_gen.v" "" { Text "E:/code/EP2C20/vbuffer1/clk_gen.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clk_gen.v(22) " "Warning: Verilog HDL assignment warning at clk_gen.v(22): truncated value with size 32 to match size of target (2)" {  } { { "clk_gen.v" "" { Text "E:/code/EP2C20/vbuffer1/clk_gen.v" 22 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "filter filter:inst8 " "Info: Elaborating entity \"filter\" for hierarchy \"filter:inst8\"" {  } { { "I2C_ALTERA.bdf" "inst8" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 1040 528 640 1136 "inst8" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 filter.v(11) " "Warning: Verilog HDL assignment warning at filter.v(11): truncated value with size 32 to match size of target (16)" {  } { { "filter.v" "" { Text "E:/code/EP2C20/vbuffer1/filter.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 filter.v(19) " "Warning: Verilog HDL assignment warning at filter.v(19): truncated value with size 32 to match size of target (1)" {  } { { "filter.v" "" { Text "E:/code/EP2C20/vbuffer1/filter.v" 19 0 0 } }  } 0}