i2c_altera.tan.qmsg

AV视频信号输入后

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] register sld_hub:sld_hub_inst\|hub_tdo 132.56 MHz 7.544 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 132.56 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.544 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.501 ns + Longest register register " "Info: + Longest register to register delay is 3.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] 1 REG LCFF_X35_Y16_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y16_N31; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.636 ns) 1.791 ns sld_hub:sld_hub_inst\|hub_tdo~297 2 COMB LCCOMB_X33_Y16_N26 1 " "Info: 2: + IC(1.155 ns) + CELL(0.636 ns) = 1.791 ns; Loc. = LCCOMB_X33_Y16_N26; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~297'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.791 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~297 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(0.210 ns) 2.664 ns sld_hub:sld_hub_inst\|hub_tdo~298 3 COMB LCCOMB_X34_Y16_N24 1 " "Info: 3: + IC(0.663 ns) + CELL(0.210 ns) = 2.664 ns; Loc. = LCCOMB_X34_Y16_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~298'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.873 ns" { sld_hub:sld_hub_inst|hub_tdo~297 sld_hub:sld_hub_inst|hub_tdo~298 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.378 ns) 3.391 ns sld_hub:sld_hub_inst\|hub_tdo~301 4 COMB LCCOMB_X34_Y16_N28 1 " "Info: 4: + IC(0.349 ns) + CELL(0.378 ns) = 3.391 ns; Loc. = LCCOMB_X34_Y16_N28; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~301'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.727 ns" { sld_hub:sld_hub_inst|hub_tdo~298 sld_hub:sld_hub_inst|hub_tdo~301 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 3.501 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LCFF_X34_Y16_N29 1 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 3.501 ns; Loc. = LCFF_X34_Y16_N29; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.110 ns" { sld_hub:sld_hub_inst|hub_tdo~301 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.334 ns 38.10 % " "Info: Total cell delay = 1.334 ns ( 38.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.167 ns 61.90 % " "Info: Total interconnect delay = 2.167 ns ( 61.90 % )" {  } {  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "3.501 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~297 sld_hub:sld_hub_inst|hub_tdo~298 sld_hub:sld_hub_inst|hub_tdo~301 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.501 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~297 sld_hub:sld_hub_inst|hub_tdo~298 sld_hub:sld_hub_inst|hub_tdo~301 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.155ns 0.663ns 0.349ns 0.000ns } { 0.000ns 0.636ns 0.210ns 0.378ns 0.110ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.765 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G2 200 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G2; Fanout = 200; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.086 ns) + CELL(0.679 ns) 1.765 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X34_Y16_N29 1 " "Info: 3: + IC(1.086 ns) + CELL(0.679 ns) = 1.765 ns; Loc. = LCFF_X34_Y16_N29; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.765 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 38.47 % " "Info: Total cell delay = 0.679 ns ( 38.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.086 ns 61.53 % " "Info: Total interconnect delay = 1.086 ns ( 61.53 % )" {  } {  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.765 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.765 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.086ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.766 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G2 200 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G2; Fanout = 200; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.679 ns) 1.766 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] 3 REG LCFF_X35_Y16_N31 3 " "Info: 3: + IC(1.087 ns) + CELL(0.679 ns) = 1.766 ns; Loc. = LCFF_X35_Y16_N31; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.766 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 38.45 % " "Info: Total cell delay = 0.679 ns ( 38.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns 61.55 % " "Info: Total interconnect delay = 1.087 ns ( 61.55 % )" {  } {  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.765 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.765 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.086ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "3.501 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~297 sld_hub:sld_hub_inst|hub_tdo~298 sld_hub:sld_hub_inst|hub_tdo~301 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.501 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~297 sld_hub:sld_hub_inst|hub_tdo~298 sld_hub:sld_hub_inst|hub_tdo~301 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.155ns 0.663ns 0.349ns 0.000ns } { 0.000ns 0.636ns 0.210ns 0.378ns 0.110ns } } } { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.765 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.765 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.086ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "PCLK register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[2\] register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[7\] 183.55 MHz 5.448 ns Internal " "Info: Clock \"PCLK\" has Internal fmax of 183.55 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[2\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[7\]\" (period= 5.448 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.178 ns + Longest register register " "Info: + Longest register to register delay is 5.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[2\] 1 REG LCFF_X32_Y16_N11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y16_N11; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[2\]'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_0a9.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_0a9.tdf" 93 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.664 ns) 1.447 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~68 2 COMB LCCOMB_X33_Y16_N6 1 " "Info: 2: + IC(0.783 ns) + CELL(0.664 ns) = 1.447 ns; Loc. = LCCOMB_X33_Y16_N6; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~68'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.447 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~68 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.388 ns) + CELL(0.664 ns) 2.499 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~69 3 COMB LCCOMB_X33_Y16_N28 1 " "Info: 3: + IC(0.388 ns) + CELL(0.664 ns) = 2.499 ns; Loc. = LCCOMB_X33_Y16_N28; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~69'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.052 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~68 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~69 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.210 ns) 3.059 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0 4 COMB LCCOMB_X33_Y16_N2 12 " "Info: 4: + IC(0.350 ns) + CELL(0.210 ns) = 3.059 ns; Loc. = LCCOMB_X33_Y16_N2; Fanout = 12; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.560 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~69 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.210 ns) 3.969 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|_~2 5 COMB LCCOMB_X32_Y16_N26 10 " "Info: 5: + IC(0.700 ns) + CELL(0.210 ns) = 3.969 ns; Loc. = LCCOMB_X32_Y16_N26; Fanout = 10; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|_~2'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.910 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|_~2 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 251 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.872 ns) 5.178 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[7\] 6 REG LCFF_X32_Y16_N21 3 " "Info: 6: + IC(0.337 ns) + CELL(0.872 ns) = 5.178 ns; Loc. = LCFF_X32_Y16_N21; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[7\]'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.209 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "db/cntr_0a9.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_0a9.tdf" 93 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.620 ns 50.60 % " "Info: Total cell delay = 2.620 ns ( 50.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.558 ns 49.40 % " "Info: Total interconnect delay = 2.558 ns ( 49.40 % )" {  } {  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "5.178 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~68 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~69 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.178 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~68 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~69 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } { 0.000ns 0.783ns 0.388ns 0.350ns 0.700ns 0.337ns } { 0.000ns 0.664ns 0.664ns 0.210ns 0.210ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PCLK destination 2.972 ns + Shortest register " "Info: + Shortest clock path from clock \"PCLK\" to destination register is 2.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns PCLK 1 CLK PIN_A12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_A12; Fanout = 1; CLK Node = 'PCLK'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { PCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 832 1680 1848 848 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns PCLK~clkctrl 2 COMB CLKCTRL_G10 137 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G10; Fanout = 137; COMB Node = 'PCLK~clkctrl'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.117 ns" { PCLK PCLK~clkctrl } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 832 1680 1848 848 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.679 ns) 2.972 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[7\] 3 REG LCFF_X32_Y16_N21 3 " "Info: 3: + IC(1.076 ns) + CELL(0.679 ns) = 2.972 ns; Loc. = LCFF_X32_Y16_N21; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[7\]'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.755 ns" { PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "db/cntr_0a9.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_0a9.tdf" 93 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 59.86 % " "Info: Total cell delay = 1.779 ns ( 59.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns 40.14 % " "Info: Total interconnect delay = 1.193 ns ( 40.14 % )" {  } {  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "2.972 ns" { PCLK PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.972 ns" { PCLK PCLK~combout PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } { 0.000ns 0.000ns 0.117ns 1.076ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PCLK source 2.972 ns - Longest register " "Info: - Longest clock path from clock \"PCLK\" to source register is 2.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns PCLK 1 CLK PIN_A12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_A12; Fanout = 1; CLK Node = 'PCLK'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { PCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 832 1680 1848 848 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns PCLK~clkctrl 2 COMB CLKCTRL_G10 137 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G10; Fanout = 137; COMB Node = 'PCLK~clkctrl'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.117 ns" { PCLK PCLK~clkctrl } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 832 1680 1848 848 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.679 ns) 2.972 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[2\] 3 REG LCFF_X32_Y16_N11 3 " "Info: 3: + IC(1.076 ns) + CELL(0.679 ns) = 2.972 ns; Loc. = LCFF_X32_Y16_N11; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_0a9:auto_generated\|safe_q\[2\]'" {  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.755 ns" { PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_0a9.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_0a9.tdf" 93 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 59.86 % " "Info: Total cell delay = 1.779 ns ( 59.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns 40.14 % " "Info: Total interconnect delay = 1.193 ns ( 40.14 % )" {  } {  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "2.972 ns" { PCLK PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.972 ns" { PCLK PCLK~combout PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.117ns 1.076ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "2.972 ns" { PCLK PCLK~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_0a9:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.972 ns" { P