i2c_altera.tan.qmsg

AV视频信号输入后

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off I2C_ALTERA -c I2C_ALTERA --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off I2C_ALTERA -c I2C_ALTERA --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SYSCLK " "Info: Assuming node \"SYSCLK\" is an undefined clock" {  } { { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 1528 160 328 1544 "SYSCLK" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SYSCLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "PCLK " "Info: Assuming node \"PCLK\" is an undefined clock" {  } { { "I2C_ALTERA.bdf" "" { Schematic "E:/code/EP2C20/vbuffer1/I2C_ALTERA.bdf" { { 832 1680 1848 848 "PCLK" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "PCLK" } } } }  } 0}  } {  } 0}