📄 i2c_altera.fit.qmsg
字号:
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.367 ns register memory " "Info: Estimated most critical path is register to memory delay of 6.367 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|safe_q\[0\] 1 REG LAB_X40_Y17 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X40_Y17; Fanout = 13; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|safe_q\[0\]'" { } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_95a:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_95a.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_95a.tdf" 94 8 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.649 ns) + CELL(0.626 ns) 1.275 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|counter_comb_bita0~COUT 2 COMB LAB_X40_Y17 2 " "Info: 2: + IC(0.649 ns) + CELL(0.626 ns) = 1.275 ns; Loc. = LAB_X40_Y17; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|counter_comb_bita0~COUT'" { } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "1.275 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_95a:auto_generated|safe_q[0] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_95a:auto_generated|counter_comb_bita0~COUT } "NODE_NAME" } "" } } { "db/cntr_95a.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_95a.tdf" 36 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.414 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|counter_comb_bita1~COUT 3 COMB LAB_X40_Y17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.139 ns) = 1.414 ns; Loc. = LAB_X40_Y17; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|counter_comb_bita1~COUT'" { } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA.quartus_db" { Floorplan "E:/code/EP2C20/vbuffer1/" "" "0.139 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_95a:auto_generated|counter_comb_bita0~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_95a:auto_generated|counter_comb_bita1~COUT } "NODE_NAME" } "" } } { "db/cntr_95a.tdf" "" { Text "E:/code/EP2C20/vbuffer1/db/cntr_95a.tdf" 41 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.553 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|counter_comb_bita2~COUT 4 COMB LAB_X40_Y17 2 " "Info: 4: + IC(0.000 ns) + CELL(0.139 ns) = 1.553 ns; Loc. = LAB_X40_Y17; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_95a:auto_generated\|counter_comb_bita2~COUT'" { } { { "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" "" { Report "E:/code/EP2C20/vbuffer1/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "E:/code/EP2C20/vbuffer1/db/I2C_ALTE
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -