📄 i2c_altera.vwf

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💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 10000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("SYSCLK")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("RST")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("SCL")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BIDIR;
	PARENT = "";
}

SIGNAL("SDA")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BIDIR;
	PARENT = "";
}

SIGNAL("SCL~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("SDA~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("altera_reserved_tdo")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("SYSCLK")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 500000;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("RST")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 715.0;
		LEVEL 0 FOR 3150.0;
		LEVEL 1 FOR 9996135.0;
	}
}

TRANSITION_LIST("SCL")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10000000.0;
	}
}

TRANSITION_LIST("SDA")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 10000000.0;
	}
}

TRANSITION_LIST("SCL~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 4200.456;
		NODE
		{
			REPEAT = 9;
			LEVEL 0 FOR 159.675;
			LEVEL Z FOR 160.325;
		}
		NODE
		{
			REPEAT = 24;
			LEVEL 0 FOR 399.675;
			NODE
			{
				REPEAT = 8;
				LEVEL Z FOR 160.325;
				LEVEL 0 FOR 159.675;
			}
			LEVEL Z FOR 160.325;
		}
		LEVEL 0 FOR 319.675;
		LEVEL Z FOR 720.325;
		NODE
		{
			REPEAT = 9;
			LEVEL 0 FOR 159.675;
			LEVEL Z FOR 160.325;
		}
		NODE
		{
			REPEAT = 32;
			LEVEL 0 FOR 399.675;
			NODE
			{
				REPEAT = 8;
				LEVEL Z FOR 160.325;
				LEVEL 0 FOR 159.675;
			}
			LEVEL Z FOR 160.325;
		}
		LEVEL 0 FOR 399.675;
		NODE
		{
			REPEAT = 8;
			LEVEL Z FOR 160.325;
			LEVEL 0 FOR 159.675;
		}
		LEVEL Z FOR 160.325;
		LEVEL 0 FOR 319.675;
		LEVEL Z FOR 9810839.869;
	}
}

TRANSITION_LIST("SDA~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 4040.424;
		LEVEL 0 FOR 559.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 639.675;
		NODE
		{
			REPEAT = 2;
			LEVEL Z FOR 320.325;
			LEVEL 0 FOR 319.675;
		}
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2479.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 1519.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 959.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 239.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 1919.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 879.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 639.675;
		LEVEL Z FOR 960.325;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 2799.675;
			LEVEL Z FOR 320.325;
		}
		LEVEL 0 FOR 239.675;
		LEVEL Z FOR 960.325;
		LEVEL 0 FOR 1599.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 1519.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 319.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 239.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 319.675;
		LEVEL Z FOR 960.325;
		LEVEL 0 FOR 959.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2479.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 239.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2239.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 559.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 959.675;
		LEVEL Z FOR 1280.325;
		LEVEL 0 FOR 559.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 1919.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2799.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2479.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 879.675;
		NODE
		{
			REPEAT = 3;
			LEVEL Z FOR 320.325;
			LEVEL 0 FOR 319.675;
		}
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 879.675;
		LEVEL Z FOR 960.325;
		LEVEL 0 FOR 959.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 1519.675;
		LEVEL Z FOR 640.325;
		LEVEL 0 FOR 639.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 239.675;
		LEVEL Z FOR 960.325;
		LEVEL 0 FOR 319.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 959.675;
		NODE
		{
			REPEAT = 5;
			LEVEL Z FOR 320.325;
			LEVEL 0 FOR 2799.675;
		}
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 399.675;
		LEVEL Z FOR 400.325;
		LEVEL 0 FOR 559.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 639.675;
		NODE
		{
			REPEAT = 2;
			LEVEL Z FOR 320.325;
			LEVEL 0 FOR 319.675;
		}
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 559.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 1919.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2159.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 319.675;
		LEVEL Z FOR 320.325;
		NODE
		{
			REPEAT = 23;
			LEVEL 0 FOR 239.675;
			LEVEL Z FOR 2880.325;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 2799.675;
			LEVEL Z FOR 320.325;
		}
		LEVEL 0 FOR 1839.675;
		LEVEL Z FOR 1280.325;
		LEVEL 0 FOR 239.675;
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 2239.675;
		NODE
		{
			REPEAT = 4;
			LEVEL Z FOR 320.325;
			LEVEL 0 FOR 2799.675;
		}
		LEVEL Z FOR 320.325;
		LEVEL 0 FOR 399.675;
		LEVEL Z FOR 9810679.901;
	}
}

TRANSITION_LIST("altera_reserved_tdo")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 10000000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "RST";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SYSCLK";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SCL";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SDA~result";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SCL~result";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SDA";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "altera_reserved_tdo";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 12320000;
	MASTER = TRUE;
}
;
💿 文件大小 2238 K
👤 上传用户 guozhongjiesg02
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

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