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从MIC输入一段音频然后

wire \inst1|shift|data~22643 ;
wire \inst1|shift|data[1]~10213 ;
wire \inst1|shift|data[1] ;
wire \inst1|wb_dat[1]~1166 ;
wire \inst1|ss[1] ;
wire \inst1|wb_dat[1]~1167 ;
wire \inst1|wb_dat[1]~1168 ;
wire \inst1|wb_dat[1]~1169 ;
wire \inst1|wb_dat_o[1] ;
wire \inst|always1~314 ;
wire \inst1|shift|data~22680 ;
wire \inst1|shift|data[60] ;
wire \inst1|wb_dat[28]~1178 ;
wire \inst1|wb_dat[28]~1179 ;
wire \inst1|wb_dat_o[28] ;
wire \inst1|shift|data~22658 ;
wire \inst1|shift|data[59] ;
wire \inst1|shift|data~22625 ;
wire \inst1|shift|data[27]~10196 ;
wire \inst1|shift|data[27] ;
wire \inst1|shift|data~22560 ;
wire \inst1|shift|data[91]~10245 ;
wire \inst1|shift|data[91] ;
wire \inst1|wb_dat[27]~1180 ;
wire \inst1|wb_dat[27]~1181 ;
wire \inst1|wb_dat_o[27] ;
wire \inst1|shift|data~22538 ;
wire \inst1|shift|data[90]~10223 ;
wire \inst1|shift|data[90] ;
wire \inst1|wb_dat[26]~1182 ;
wire \inst1|shift|always3~11508 ;
wire \inst1|shift|data[122] ;
wire \inst1|wb_dat[26]~1183 ;
wire \inst1|wb_dat_o[26] ;
wire \inst|always1~315 ;
wire \inst|always1~316 ;
wire \inst1|ctrl~273 ;
wire \inst1|ctrl[8] ;
wire \inst1|wb_dat_o[8]~130 ;
wire \inst1|wb_dat[8]~1217 ;
wire \inst1|wb_dat_o[8] ;
wire \inst|next.111~19 ;
wire \inst|next.001~28 ;
wire \inst|STATE.001 ;
wire \inst|STATE.010 ;
wire \inst|next.011~17 ;
wire \inst|STATE.011 ;
wire \inst|Select~1079 ;
wire \inst|Select~1082 ;
wire \inst|Select~1084 ;
wire \inst|wb_adr[4] ;
wire \inst1|always5~21 ;
wire \inst1|ctrl~274 ;
wire \inst1|ctrl[0] ;
wire \inst1|shift|cnt~216 ;
wire \inst1|shift|cnt[0] ;
wire \inst1|shift|add~1944 ;
wire \inst1|shift|add~1945 ;
wire \inst1|shift|cnt[7]~131 ;
wire \inst1|shift|reduce_or~104 ;
wire \inst1|shift|reduce_or~0 ;
wire \inst1|shift|cnt[7] ;
wire \inst1|shift|reduce_or~103 ;
wire \inst1|shift|tip~48 ;
wire \inst1|shift|tip ;
wire \inst1|ctrl[13] ;
wire \inst1|ss[0] ;
wire \inst1|ss_pad_o~42 ;
wire \altera_reserved_tms~combout ;
wire \altera_internal_jtag~TDO ;
wire \inst1|shift|add~1948 ;
wire \inst1|shift|add~1950 ;
wire \inst1|shift|add~1952 ;
wire \inst1|shift|add~1954 ;
wire \inst1|shift|add~1956 ;
wire \inst1|shift|add~1958 ;
wire \inst1|shift|add~1965 ;
wire \inst1|shift|add~1967 ;
wire \inst1|shift|add~1957 ;
wire \inst1|shift|add~1959 ;
wire \inst1|shift|add~1955 ;
wire \inst1|shift|add~1960 ;
wire \inst1|shift|data~22639 ;
wire \inst1|shift|data[6]~10209 ;
wire \inst1|shift|data[6] ;
wire \inst1|shift|add~1947 ;
wire \inst1|shift|add~1964 ;
wire \inst1|shift|add~1949 ;
wire \inst1|shift|add~1963 ;
wire \inst1|shift|Mux~1481 ;
wire \inst1|shift|Mux~1482 ;
wire \inst1|shift|add~1953 ;
wire \inst1|shift|add~1962 ;
wire \inst1|shift|data~22644 ;
wire \inst1|shift|data[2]~10214 ;
wire \inst1|shift|data[2] ;
wire \inst1|shift|Mux~1483 ;
wire \inst1|shift|Mux~1484 ;
wire \inst1|shift|Mux~1485 ;
wire \inst1|shift|data~22635 ;
wire \inst1|shift|data[9]~10205 ;
wire \inst1|shift|data[9] ;
wire \inst1|shift|data~22636 ;
wire \inst1|shift|data[10]~10206 ;
wire \inst1|shift|data[10] ;
wire \inst1|shift|Mux~1479 ;
wire \inst1|shift|Mux~1480 ;
wire \inst1|shift|Mux~1486 ;
wire \inst1|shift|Mux~1487 ;
wire \inst1|shift|Mux~1488 ;
wire \inst1|shift|add~1935 ;
wire \inst1|shift|add~1951 ;
wire \inst1|shift|add~1961 ;
wire \inst1|shift|data~22627 ;
wire \inst1|shift|data[18]~10198 ;
wire \inst1|shift|data[18] ;
wire \inst1|shift|Mux~1473 ;
wire \inst1|shift|data~22629 ;
wire \inst1|shift|data[19]~10200 ;
wire \inst1|shift|data[19] ;
wire \inst1|shift|Mux~1474 ;
wire \inst1|shift|data~22622 ;
wire \inst1|shift|data[25]~10193 ;
wire \inst1|shift|data[25] ;
wire \inst1|shift|data~22623 ;
wire \inst1|shift|data[26]~10194 ;
wire \inst1|shift|data[26] ;
wire \inst1|shift|Mux~1471 ;
wire \inst1|shift|Mux~1472 ;
wire \inst1|shift|Mux~1475 ;
wire \inst1|shift|data~22618 ;
wire \inst1|shift|data[22]~10189 ;
wire \inst1|shift|data[22] ;
wire \inst1|shift|data~22620 ;
wire \inst1|shift|data[20]~10191 ;
wire \inst1|shift|data[20] ;
wire \inst1|shift|Mux~1469 ;
wire \inst1|shift|Mux~1470 ;
wire \inst1|shift|Mux~1478 ;
wire \inst1|shift|Mux~1489 ;
wire \inst1|shift|data~22614 ;
wire \inst1|shift|data~22615 ;
wire \inst1|shift|data~22616 ;
wire \inst1|shift|data[47] ;
wire \inst1|shift|Mux~1466 ;
wire \inst1|shift|Mux~1467 ;
wire \inst1|shift|data~22569 ;
wire \inst1|shift|data~22570 ;
wire \inst1|shift|data~22571 ;
wire \inst1|shift|data[37] ;
wire \inst1|shift|Mux~1459 ;
wire \inst1|shift|Mux~1460 ;
wire \inst1|shift|data~22584 ;
wire \inst1|shift|data~22585 ;
wire \inst1|shift|data~22586 ;
wire \inst1|shift|data[38] ;
wire \inst1|shift|Mux~1461 ;
wire \inst1|shift|Mux~1462 ;
wire \inst1|shift|Mux~1463 ;
wire \inst1|shift|Mux~1464 ;
wire \inst1|shift|Mux~1465 ;
wire \inst1|shift|Mux~1468 ;
wire \inst1|shift|Mux~1500 ;
wire \inst1|shift|Mux~1417 ;
wire \inst1|shift|Mux~1418 ;
wire \inst1|shift|data~22540 ;
wire \inst1|shift|data[82]~10225 ;
wire \inst1|shift|data[82] ;
wire \inst1|shift|Mux~1421 ;
wire \inst1|shift|Mux~1422 ;
wire \inst1|shift|Mux~1419 ;
wire \inst1|shift|Mux~1420 ;
wire \inst1|shift|Mux~1423 ;
wire \inst1|shift|Mux~1426 ;
wire \inst1|shift|always3~11540 ;
wire \inst1|shift|data[107] ;
wire \inst1|shift|Mux~1448 ;
wire \inst1|shift|Mux~1449 ;
wire \inst1|shift|Mux~1455 ;
wire \inst1|shift|always3~11549 ;
wire \inst1|shift|data[111] ;
wire \inst1|shift|Mux~1456 ;
wire \inst1|shift|Mux~1457 ;
wire \inst1|shift|always3~11538 ;
wire \inst1|shift|data[124] ;
wire \inst1|shift|data~22558 ;
wire \inst1|shift|data[92]~10243 ;
wire \inst1|shift|data[92] ;
wire \inst1|shift|Mux~1444 ;
wire \inst1|shift|Mux~1445 ;
wire \inst1|shift|data~22557 ;
wire \inst1|shift|data[64]~10242 ;
wire \inst1|shift|data[64] ;
wire \inst1|shift|Mux~1441 ;
wire \inst1|shift|Mux~1442 ;
wire \inst1|shift|Mux~1443 ;
wire \inst1|shift|always3~11529 ;
wire \inst1|shift|data[116] ;
wire \inst1|shift|Mux~1438 ;
wire \inst1|shift|Mux~1446 ;
wire \inst1|shift|always3~11523 ;
wire \inst1|shift|data[113] ;
wire \inst1|shift|Mux~1431 ;
wire \inst1|shift|Mux~1432 ;
wire \inst1|shift|Mux~1429 ;
wire \inst1|shift|Mux~1430 ;
wire \inst1|shift|Mux~1433 ;
wire \inst1|shift|always3~11525 ;
wire \inst1|shift|data[109] ;
wire \inst1|shift|data[93]~10235 ;
wire \inst1|shift|data[93] ;
wire \inst1|shift|Mux~1434 ;
wire \inst1|shift|Mux~1435 ;
wire \inst1|shift|data~22544 ;
wire \inst1|shift|data[89]~10229 ;
wire \inst1|shift|data[89] ;
wire \inst1|shift|Mux~1427 ;
wire \inst1|shift|Mux~1428 ;
wire \inst1|shift|Mux~1436 ;
wire \inst1|shift|Mux~1447 ;
wire \inst1|shift|Mux~1458 ;
wire \inst1|shift|Mux~1501 ;
wire \inst1|shift|s_out~149 ;
wire \inst1|shift|s_out ;

wire [2:0] \inst3|altpll_component|pll_CLK_bus ;
wire [15:0] \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus ;
wire [15:0] \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus ;

assign \inst3|altpll_component|_clk0  = \inst3|altpll_component|pll_CLK_bus [0];
assign \inst3|altpll_component|pll~CLK1  = \inst3|altpll_component|pll_CLK_bus [1];
assign \inst3|altpll_component|pll~CLK2  = \inst3|altpll_component|pll_CLK_bus [2];

assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[0]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [0];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[1]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [1];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[2]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [2];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[3]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [3];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[4]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [4];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[5]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [5];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[6]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [6];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[7]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [7];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[8]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [8];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[9]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [9];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[10]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [10];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[11]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [11];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[12]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [12];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[13]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [13];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[14]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [14];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[15]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus [15];

assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[0]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [0];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[1]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [1];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[2]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [2];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[3]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [3];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[4]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [4];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[5]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [5];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[6]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [6];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[7]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [7];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[8]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [8];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[9]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [9];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[10]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [10];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[11]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [11];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[12]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [12];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[13]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [13];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[14]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [14];
assign \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[15]  = \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus [15];

// atom is at M4K_X17_Y17
cycloneii_ram_block \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 (
	.portawe(gnd),
	.portaaddrstall(gnd),
	.portbrewe(\inst2|altsyncram_component|auto_generated|mgl_prim2|enable_write~11 ),
	.portbaddrstall(gnd),
	.clk0(\inst3|altpll_component|_clk0~clkctrl ),
	.clk1(\altera_internal_jtag~TCKUTAPclkctrl ),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
	.portaaddr({\~GND ,\inst|r_rom_rab_reg[3]~84 ,\inst|r_rom_rab_reg[2]~83 ,\inst|r_rom_rab_reg[1]~82 ,\inst|r_rom_rab_reg[0]~81 }),
	.portabyteenamasks(),
	.portbdatain({\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[14] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[13] ,
\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[12] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[11] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[10] ,
\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[9] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[8] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7] ,
\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[4] ,
\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[3] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[2] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[1] ,
\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0] }),
	.portbaddr({\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2] ,
\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1] ,\inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0] }),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTADATAOUT_bus ),
	.portbdataout(\inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .operation_mode = "bidir_dual_port";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_block_type = "M4K";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .mixed_port_feed_through_mode = "dont_care";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .logical_ram_name = "SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_acs:auto_generated|altsyncram_o2a2:altsyncram1|ALTSYNCRAM";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .init_file = "Aic23Regs.mif";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .init_file_layout = "port_a";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .data_interleave_width_in_bits = 1;
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .data_interleave_offset_in_bits = 1;
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_byte_enable_clock = "none";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_logical_ram_depth = 32;
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_logical_ram_width = 16;
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_data_in_clear = "none";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_address_clear = "none";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_write_enable_clear = "none";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_byte_enable_clear = "none";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_data_out_clock = "clock0";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_data_out_clear = "none";
defparam \inst2|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .port_a_first_address = 0;
defparam \inst2|altsyncram_component|auto_