i2c_altera.vo

从MIC输入一段音频然后

wire \sld_hub_inst|jtag_state_machine|state~11 ;
wire \sld_hub_inst|jtag_state_machine|state[4] ;
wire \sld_hub_inst|jtag_state_machine|state~14 ;
wire \sld_hub_inst|jtag_state_machine|state[5] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|enable_write~11 ;
wire \SYSCLK~combout ;
wire \inst3|altpll_component|_clk0 ;
wire \inst3|altpll_component|_clk0~clkctrl ;
wire \altera_internal_jtag~TCKUTAP ;
wire \altera_internal_jtag~TCKUTAPclkctrl ;
wire \inst|r_rom_rab_reg[0]~81 ;
wire \inst|r_rom_rab_reg[1]~82 ;
wire \inst|r_rom_rab_reg[2]~83 ;
wire \inst|r_rom_rab_reg[3]~84 ;
wire \~GND ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|process1~1 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[15] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1345 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15]~1339 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[14] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1343 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[14] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[13] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1340 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[13] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[12] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1346 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[12] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[11] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1347 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[11] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[10] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1348 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[10] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[9] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1349 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[9] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[8] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1342 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[8] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[7] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1350 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[6] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1351 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[5] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1352 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[4] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1353 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[4] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[3] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1354 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[3] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1344 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1341 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[1] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[0] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1338 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[11] ;
wire \inst|Select~1094 ;
wire \inst|wb_wdb[11] ;
wire \inst1|wb_ack_o~1 ;
wire \inst1|wb_ack_o ;
wire \inst|wb_we~78 ;
wire \inst|wb_we~79 ;
wire \inst|wb_we ;
wire \inst|STATE.111~feeder ;
wire \inst|next.111~20 ;
wire \inst|STATE.111 ;
wire \inst|always9~0 ;
wire \inst|wb_cyc ;
wire \inst1|always4~33 ;
wire \inst|Select~1081 ;
wire \inst|wb_adr[3] ;
wire \inst1|always5~1 ;
wire \inst1|ctrl[11] ;
wire \inst1|wb_dat_o[11]~127 ;
wire \inst|Select~1085 ;
wire \inst|Select~1086 ;
wire \inst|wb_adr[2] ;
wire \inst1|wb_dat_o[14]~190 ;
wire \inst1|always4~1 ;
wire \inst1|divider[11] ;
wire \inst1|shift|always3~1 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[3] ;
wire \inst|Select~1101 ;
wire \inst|wb_wdb[3] ;
wire \inst1|ctrl[3] ;
wire \inst1|shift|cnt~213 ;
wire \inst|Select~1095 ;
wire \inst|wb_wdb[10] ;
wire \inst1|divider[10] ;
wire \inst|wb_wdb[4]~240 ;
wire \inst|Select~1088 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[8] ;
wire \inst|Select~1089 ;
wire \inst|Select~1090 ;
wire \inst|wb_wdb[8] ;
wire \inst1|divider[8] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[9] ;
wire \inst|Select~1096 ;
wire \inst|wb_wdb[9] ;
wire \inst1|divider[9] ;
wire \inst1|clgen|reduce_or~114 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[1] ;
wire \inst|Select~1103 ;
wire \inst|wb_wdb[1] ;
wire \inst1|divider[1] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[0] ;
wire \inst|Select~1078 ;
wire \inst|wb_wdb[0] ;
wire \inst1|divider[0] ;
wire \inst1|divider[3] ;
wire \inst1|clgen|reduce_or~116 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[14] ;
wire \inst|Select~1092 ;
wire \inst|wb_wdb[14] ;
wire \inst1|divider[14] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[12] ;
wire \inst|Select~1093 ;
wire \inst|wb_wdb[12] ;
wire \inst1|divider[12] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[15] ;
wire \inst|Select~1091 ;
wire \inst|wb_wdb[15] ;
wire \inst1|divider[15] ;
wire \inst1|clgen|reduce_or~113 ;
wire \inst1|clgen|reduce_or~117 ;
wire \inst1|clgen|pos_edge~109 ;
wire \inst1|clgen|pos_edge~110 ;
wire \inst1|clgen|pos_edge ;
wire \inst1|shift|cnt[6]~210 ;
wire \inst1|shift|cnt[3] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[5] ;
wire \inst|Select~1099 ;
wire \inst|wb_wdb[5] ;
wire \inst1|ctrl[5] ;
wire \inst1|shift|cnt~211 ;
wire \inst1|shift|cnt[5] ;
wire \inst1|shift|add~1932 ;
wire \inst1|shift|add~1934 ;
wire \inst1|shift|add~1936 ;
wire \inst1|shift|add~1938 ;
wire \inst1|shift|add~1939 ;
wire \inst1|shift|cnt~212 ;
wire \inst1|shift|cnt[4] ;
wire \inst1|shift|add~1940 ;
wire \inst1|shift|add~1942 ;
wire \inst1|shift|add~1943 ;
wire \inst1|shift|cnt~209 ;
wire \inst1|shift|cnt[6] ;
wire \inst1|shift|reduce_or~102 ;
wire \inst1|clgen|clk_out~138 ;
wire \inst1|clgen|clk_out~139 ;
wire \inst1|clgen|clk_out ;
wire \inst1|clgen|cnt[0]~336 ;
wire \inst1|divider[0]~96 ;
wire \inst1|clgen|cnt[3]~342 ;
wire \inst1|divider[3]~105 ;
wire \inst1|clgen|cnt[3] ;
wire \inst1|clgen|cnt_one~108 ;
wire \inst1|clgen|cnt_zero ;
wire \inst1|clgen|always0~0 ;
wire \inst1|clgen|cnt[0] ;
wire \inst1|clgen|cnt[0]~337 ;
wire \inst1|clgen|cnt[1]~338 ;
wire \inst1|divider[1]~103 ;
wire \inst1|clgen|cnt[1] ;
wire \inst1|clgen|cnt[1]~339 ;
wire \inst1|clgen|cnt[2]~340 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[2] ;
wire \inst|Select~1102 ;
wire \inst|wb_wdb[2] ;
wire \inst1|divider[2] ;
wire \inst1|divider[2]~104 ;
wire \inst1|clgen|cnt[2] ;
wire \inst1|clgen|cnt[2]~341 ;
wire \inst1|clgen|cnt[3]~343 ;
wire \inst1|clgen|cnt[4]~344 ;
wire \inst1|divider[4] ;
wire \inst1|divider[4]~106 ;
wire \inst1|clgen|cnt[4] ;
wire \inst1|clgen|cnt[4]~345 ;
wire \inst1|clgen|cnt[5]~347 ;
wire \inst1|clgen|cnt[6]~349 ;
wire \inst1|clgen|cnt[7]~350 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[7] ;
wire \inst|Select~1097 ;
wire \inst|wb_wdb[7] ;
wire \inst1|divider[7] ;
wire \inst1|divider[7]~109 ;
wire \inst1|clgen|cnt[7] ;
wire \inst1|clgen|cnt[7]~351 ;
wire \inst1|clgen|cnt[8]~353 ;
wire \inst1|clgen|cnt[9]~354 ;
wire \inst1|divider[9]~111 ;
wire \inst1|clgen|cnt[9] ;
wire \inst1|clgen|cnt[9]~355 ;
wire \inst1|clgen|cnt[10]~357 ;
wire \inst1|clgen|cnt[11]~358 ;
wire \inst1|divider[11]~98 ;
wire \inst1|clgen|cnt[11] ;
wire \inst1|clgen|cnt[11]~359 ;
wire \inst1|clgen|cnt[12]~361 ;
wire \inst1|clgen|cnt[13]~362 ;
wire \inst|Select~1087 ;
wire \inst|wb_wdb[13] ;
wire \inst1|divider[13] ;
wire \inst1|divider[13]~100 ;
wire \inst1|clgen|cnt[13] ;
wire \inst1|clgen|cnt[13]~363 ;
wire \inst1|clgen|cnt[14]~364 ;
wire \inst1|divider[14]~101 ;
wire \inst1|clgen|cnt[14] ;
wire \inst1|clgen|cnt[14]~365 ;
wire \inst1|clgen|cnt[15]~366 ;
wire \inst1|divider[15]~102 ;
wire \inst1|clgen|cnt[15] ;
wire \inst1|clgen|cnt_one~111 ;
wire \inst1|clgen|cnt_one ;
wire \inst1|clgen|neg_edge~19 ;
wire \inst1|clgen|neg_edge ;
wire \inst1|ctrl[9] ;
wire \inst1|shift|rx_clk~124 ;
wire \inst1|shift|add~1968 ;
wire \inst1|shift|add~1974 ;
wire \inst1|shift|add~1931 ;
wire \inst1|shift|add~1990 ;
wire \inst1|shift|add~1991 ;
wire \inst1|shift|always3~11550 ;
wire \inst1|shift|always3~3 ;
wire \inst1|shift|data[126]~22533 ;
wire \inst1|shift|data[127] ;
wire \inst1|ctrl[2] ;
wire \inst1|shift|cnt~214 ;
wire \inst1|shift|cnt[2] ;
wire \inst1|shift|add~1933 ;
wire \inst1|ctrl[1] ;
wire \inst1|shift|cnt~215 ;
wire \inst1|shift|cnt[1] ;
wire \inst1|shift|add~1969 ;
wire \inst1|shift|add~1971 ;
wire \inst1|shift|add~1972 ;
wire \inst1|shift|add~1975 ;
wire \inst1|shift|add~1977 ;
wire \inst1|shift|add~1978 ;
wire \inst1|shift|add~1981 ;
wire \inst1|shift|always3~11547 ;
wire \inst1|shift|data[115] ;
wire \inst1|shift|add~1937 ;
wire \inst1|shift|add~1986 ;
wire \inst1|shift|add~1979 ;
wire \inst1|shift|add~1984 ;
wire \inst1|shift|add~1987 ;
wire \inst1|shift|Mux~1540 ;
wire \inst1|shift|Mux~1541 ;
wire \inst1|shift|add~1988 ;
wire \inst1|shift|add~1976 ;
wire \inst1|shift|add~1989 ;
wire \inst1|shift|add~1941 ;
wire \inst1|shift|add~2002 ;
wire \inst1|shift|add~1973 ;
wire \inst1|shift|add~1983 ;
wire \inst1|shift|add~1993 ;
wire \inst1|shift|add~1998 ;
wire \inst1|shift|add~1985 ;
wire \inst1|shift|add~1995 ;
wire \inst1|shift|add~2000 ;
wire \inst1|shift|add~2003 ;
wire \inst1|shift|add~2008 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[6] ;
wire \inst|Select~1098 ;
wire \inst|wb_wdb[6] ;
wire \inst1|ctrl[6] ;
wire \inst1|shift|add~2001 ;
wire \inst1|shift|add~2006 ;
wire \inst1|shift|add~2009 ;
wire \inst1|shift|Decoder~2523 ;
wire \inst1|shift|always3~11530 ;
wire \inst1|shift|always3~11532 ;
wire \inst1|shift|data[120] ;
wire \inst1|shift|Decoder~2524 ;
wire \inst1|shift|always3~11533 ;
wire \inst1|shift|always3~11535 ;
wire \inst1|shift|data[112] ;
wire \inst1|shift|Mux~1537 ;
wire \inst1|shift|Mux~1538 ;
wire \inst1|shift|always3~11514 ;
wire \inst1|shift|data[126] ;
wire \inst1|shift|always3~11505 ;
wire \inst1|shift|data[118] ;
wire \inst1|shift|Mux~1535 ;
wire \inst1|shift|Mux~1536 ;
wire \inst1|shift|Mux~1539 ;
wire \inst1|shift|Mux~1542 ;
wire \inst1|shift|always3~11504 ;
wire \inst1|shift|data[102] ;
wire \inst1|shift|Mux~1512 ;
wire \inst1|shift|Mux~1513 ;
wire \inst1|shift|always3~11516 ;
wire \inst1|shift|data[105] ;
wire \inst1|shift|always3~11531 ;
wire \inst1|shift|data[104] ;
wire \inst1|shift|Mux~1514 ;
wire \inst1|shift|Mux~1515 ;
wire \inst1|shift|always3~11522 ;
wire \inst1|shift|data[97] ;
wire \inst1|shift|Decoder~2516 ;
wire \inst1|shift|always3~11509 ;
wire \inst1|shift|always3~11510 ;
wire \inst1|shift|data[98] ;