i2c_altera.vo

从MIC输入一段音频然后

wire \inst1|shift|add~1982 ;
wire \inst1|shift|Mux~1502 ;
wire \inst1|shift|Mux~1503 ;
wire \inst1|shift|Mux~1504 ;
wire \inst1|shift|Mux~1505 ;
wire \inst1|shift|Mux~1506 ;
wire \inst1|shift|Mux~1507 ;
wire \inst1|shift|Mux~1508 ;
wire \inst1|shift|Mux~1509 ;
wire \inst1|shift|Mux~1510 ;
wire \inst1|shift|Mux~1511 ;
wire \inst1|shift|add~1992 ;
wire \inst1|shift|Mux~1519 ;
wire \inst1|shift|Mux~1520 ;
wire \inst1|shift|add~1999 ;
wire \inst1|shift|Mux~1533 ;
wire \inst1|shift|Mux~1534 ;
wire \inst1|shift|Mux~1554 ;
wire \inst1|shift|Mux~1555 ;
wire \inst1|shift|Mux~1556 ;
wire \inst1|shift|Mux~1557 ;
wire \inst1|shift|add~2004 ;
wire \inst1|shift|always3~11503 ;
wire \inst1|shift|data~22537 ;
wire \inst1|shift|data~22541 ;
wire \inst1|shift|always3~11512 ;
wire \inst1|shift|always3~11513 ;
wire \inst1|shift|data~22542 ;
wire \inst1|shift|data~22543 ;
wire \inst1|shift|data[78]~10228 ;
wire \inst1|shift|always3~11515 ;
wire \inst1|shift|data~22545 ;
wire \inst1|shift|data[73]~10230 ;
wire \inst1|shift|always3~11517 ;
wire \inst1|shift|always3~11518 ;
wire \inst1|shift|data~22546 ;
wire \inst1|shift|data[85]~10231 ;
wire \inst1|shift|always3~11520 ;
wire \inst1|shift|data~22548 ;
wire \inst1|shift|data[81]~10233 ;
wire \inst1|shift|always3~11521 ;
wire \inst1|shift|always3~11524 ;
wire \inst1|shift|data~22550 ;
wire \inst1|shift|data~22551 ;
wire \inst1|shift|data[77]~10236 ;
wire \inst1|shift|always3~11526 ;
wire \inst1|shift|always3~11527 ;
wire \inst1|shift|data~22552 ;
wire \inst1|shift|data[84]~10237 ;
wire \inst1|shift|data~22553 ;
wire \inst1|shift|data[68]~10238 ;
wire \inst1|shift|data~22554 ;
wire \inst1|shift|data[88]~10239 ;
wire \inst1|shift|data~22556 ;
wire \inst1|shift|data[80]~10241 ;
wire \inst1|shift|always3~11534 ;
wire \inst1|shift|always3~11539 ;
wire \inst1|shift|data~22561 ;
wire \inst1|shift|always3~11541 ;
wire \inst1|shift|always3~11542 ;
wire \inst1|shift|always3~11543 ;
wire \inst1|shift|data~22563 ;
wire \inst1|shift|data[71]~10248 ;
wire \inst1|shift|data~22564 ;
wire \inst1|shift|always3~11545 ;
wire \inst1|shift|data~22565 ;
wire \inst1|shift|always3~11548 ;
wire \inst1|shift|data~22566 ;
wire \inst1|shift|data[95]~10251 ;
wire \inst1|shift|data~22599 ;
wire \inst1|shift|data~22600 ;
wire \inst1|shift|data~22601 ;
wire \inst1|shift|data~22608 ;
wire \inst1|shift|data~22626 ;
wire \inst1|shift|data[17]~10197 ;
wire \inst1|shift|data~22628 ;
wire \inst1|shift|data[16]~10199 ;
wire \inst1|shift|data~22631 ;
wire \inst1|shift|data[29]~10202 ;
wire \inst1|shift|data~22651 ;
wire \inst1|shift|data~22652 ;
wire \inst1|shift|data~22657 ;
wire \inst1|shift|data~22659 ;
wire \inst1|shift|data~22663 ;
wire \inst1|shift|data~22665 ;
wire \inst1|shift|data~22669 ;
wire \inst1|shift|data~22670 ;
wire \inst1|shift|data~22671 ;
wire \inst1|shift|data~22672 ;
wire \inst1|shift|data~22673 ;
wire \inst1|shift|data~22677 ;
wire \inst1|shift|data~22679 ;
wire \inst1|shift|data~22681 ;
wire \inst1|shift|data~22682 ;
wire \sld_hub_inst|jtag_state_machine|state[14] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~192 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~193 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[3] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR~146 ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt~4 ;
wire \sld_hub_inst|jtag_state_machine|state[13] ;
wire \sld_hub_inst|jtag_state_machine|state~28 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~194 ;
wire \sld_hub_inst|jtag_state_machine|state~26 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1]~207 ;
wire \inst1|divider[10]~97 ;
wire \inst1|divider[12]~99 ;
wire \inst1|divider[5]~107 ;
wire \inst1|divider[6]~108 ;
wire \inst1|divider[8]~110 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|clear_signal~clkctrl ;
wire \SYSCLK~clkctrl ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[1]~feeder ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[2]~feeder ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[2]~feeder ;
wire \DOUT~combout ;
wire \inst1|ctrl[0]~feeder ;
wire \RST~combout ;
wire \inst8|rst_out~feeder ;
wire \inst8|rst_out ;
wire \inst8|rst_out~clkctrl ;
wire \inst|last_time~feeder ;
wire \inst|r_rom_rab_reg[3]~80 ;
wire \inst|r_rom_rab_reg[0]~77 ;
wire \inst|always5~0 ;
wire \inst|r_rom_rab_reg[0] ;
wire \inst|r_rom_rab_reg[1]~78 ;
wire \inst|r_rom_rab_reg[1]~74 ;
wire \inst|r_rom_rab_reg[1] ;
wire \inst|r_rom_rab_reg[2]~75 ;
wire \inst|r_rom_rab_reg[2]~79 ;
wire \inst|r_rom_rab_reg[2] ;
wire \inst|r_rom_rab_reg[3]~76 ;
wire \inst|r_rom_rab_reg[3] ;
wire \inst|reduce_nor~44 ;
wire \inst|last_time ;
wire \inst|STATE.000~feeder ;
wire \inst|STATE.000 ;
wire \inst|Select~1100 ;
wire \inst|state5_cnt[1]~32 ;
wire \inst|state5_cnt[0]~33 ;
wire \inst|state5_cnt[0] ;
wire \inst|state5_cnt[1]~31 ;
wire \inst|state5_cnt[1] ;
wire \inst|next.101~20 ;
wire \inst|first_time~feeder ;
wire \inst|first_time ;
wire \inst|next.100~57 ;
wire \inst|next.100~58 ;
wire \inst|STATE.100 ;
wire \inst|next.101~21 ;
wire \inst|STATE.101 ;
wire \sld_hub_inst|jtag_state_machine|state~15 ;
wire \altera_reserved_tck~combout ;
wire \altera_reserved_tdi~combout ;
wire altera_internal_jtag;
wire \sld_hub_inst|jtag_state_machine|state~21 ;
wire \sld_hub_inst|jtag_state_machine|state[10] ;
wire \sld_hub_inst|jtag_state_machine|state~22 ;
wire \sld_hub_inst|jtag_state_machine|state[11] ;
wire \sld_hub_inst|jtag_state_machine|state~412 ;
wire \sld_hub_inst|jtag_state_machine|state[12] ;
wire \sld_hub_inst|jtag_state_machine|state~29 ;
wire \sld_hub_inst|jtag_state_machine|state[15] ;
wire \sld_hub_inst|jtag_state_machine|state~5 ;
wire \sld_hub_inst|jtag_state_machine|state[1] ;
wire \sld_hub_inst|jtag_state_machine|state~18 ;
wire \sld_hub_inst|jtag_state_machine|state[8] ;
wire \sld_hub_inst|jtag_state_machine|state~413 ;
wire \sld_hub_inst|jtag_state_machine|state[2] ;
wire \sld_hub_inst|process0~0 ;
wire \sld_hub_inst|jtag_state_machine|state[9] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt~0 ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[0] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt~1 ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[1] ;
wire \sld_hub_inst|jtag_state_machine|state~410 ;
wire \sld_hub_inst|jtag_state_machine|state~411 ;
wire \sld_hub_inst|jtag_state_machine|state[0] ;
wire \sld_hub_inst|jtag_state_machine|state[0]~clkctrl ;
wire \sld_hub_inst|jtag_ir_register|dffs[9] ;
wire \sld_hub_inst|jtag_ir_register|dffs[8] ;
wire \sld_hub_inst|jtag_ir_register|dffs[7] ;
wire \sld_hub_inst|jtag_ir_register|dffs[6]~feeder ;
wire \sld_hub_inst|jtag_ir_register|dffs[6] ;
wire \sld_hub_inst|jtag_ir_register|dffs[5]~feeder ;
wire \sld_hub_inst|jtag_ir_register|dffs[5] ;
wire \sld_hub_inst|jtag_ir_register|dffs[4]~feeder ;
wire \sld_hub_inst|jtag_ir_register|dffs[4] ;
wire \sld_hub_inst|jtag_ir_register|dffs[3] ;
wire \sld_hub_inst|jtag_ir_register|dffs[2] ;
wire \sld_hub_inst|reduce_nor~57 ;
wire \sld_hub_inst|jtag_ir_register|dffs[1]~feeder ;
wire \sld_hub_inst|jtag_ir_register|dffs[1] ;
wire \sld_hub_inst|reduce_nor~56 ;
wire \sld_hub_inst|reduce_nor~1 ;
wire \sld_hub_inst|jtag_debug_mode_usr1 ;
wire \sld_hub_inst|HUB_BYPASS_REG~11 ;
wire \sld_hub_inst|reduce_nor~0 ;
wire \sld_hub_inst|jtag_debug_mode_usr0 ;
wire \sld_hub_inst|jtag_debug_mode~2 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode18w[3] ;
wire \sld_hub_inst|comb~66 ;
wire \sld_hub_inst|comb~67 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[1] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode28w[3] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[2] ;
wire \sld_hub_inst|OK_TO_UPDATE_IR_Q~0 ;
wire \sld_hub_inst|process2~0 ;
wire \sld_hub_inst|OK_TO_UPDATE_IR_Q ;
wire \sld_hub_inst|comb~68 ;
wire \sld_hub_inst|BROADCAST_ENA~27 ;
wire \sld_hub_inst|BROADCAST|Q[0] ;
wire \sld_hub_inst|jtag_debug_mode~171 ;
wire \sld_hub_inst|jtag_debug_mode~172 ;
wire \sld_hub_inst|jtag_debug_mode ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|no_name_gen~26 ;
wire \sld_hub_inst|IRSR_D[2]~50 ;
wire \sld_hub_inst|IRSR|Q[0]~109 ;
wire \sld_hub_inst|IRSR|Q[0]~110 ;
wire \sld_hub_inst|IRSR|Q[2] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[2]~feeder ;
wire \sld_hub_inst|IRF_ENA_ENABLE~21 ;
wire \sld_hub_inst|IRF_ENA|Q[0] ;
wire \sld_hub_inst|GEN_SHADOW_IRF~0 ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[2] ;
wire \sld_hub_inst|IRF_D[1][2]~41 ;
wire \sld_hub_inst|IRF_ENA_0|Q[0]~3 ;
wire \sld_hub_inst|IRF_ENA_0|Q[0] ;
wire \sld_hub_inst|IRF_ENABLE[1]~76 ;
wire \sld_hub_inst|IRF_ENABLE[1]~77 ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[2] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1]~feeder ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1] ;
wire \sld_hub_inst|IRF_D[1][1]~40 ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|process1~3 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0]~97 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~98 ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[3] ;
wire \sld_hub_inst|IRF_D[1][3]~43 ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[3] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[3]~clkctrl ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|reduce_nor~1 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~99 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~101 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~102 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0]~96 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~100 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~39 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~0 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~75 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~76 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~77 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~78 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2]~79 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2]~80 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3]~81 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3]~82 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4]~83 ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[4] ;
wire \sld_hub_inst|IRF_D[1][4]~44 ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[4] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg~6 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg ;
wire \sld_hub_inst|IRSR_D[0]~47 ;
wire \sld_hub_inst|IRSR|Q[0] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0]~feeder ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0] ;
wire \sld_hub_inst|IRF_D[1][0]~42 ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[0] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[0]~clkctrl ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|process0~11 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0]~feeder ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|process4~12 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0] ;
wire \sld_hub_inst|IRSR_D[1]~48 ;
wire \sld_hub_inst|IRSR|Q[1] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode78w[3] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[7] ;
wire \sld_hub_inst|comb~6 ;
wire \sld_hub_inst|RESET|Q[0] ;
wire \sld_hub_inst|CLEAR_SIGNAL~0 ;
wire \sld_hub_inst|CLEAR_SIGNAL~0clkctrl ;
wire \sld_hub_inst|jtag_state_machine|state~10 ;
wire \sld_hub_inst|jtag_state_machine|state[3] ;
wire \sld_hub_inst|IRSR_ENA ;
wire \sld_hub_inst|IRSR|Q[5] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3]~feeder ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3] ;
wire \sld_hub_inst|IRSR_D[4]~51 ;
wire \sld_hub_inst|IRSR|Q[4] ;
wire \sld_hub_inst|IRSR_D[3]~49 ;
wire \sld_hub_inst|IRSR|Q[3] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode1w[3] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[0] ;
wire \sld_hub_inst|HUB_BYPASS_REG ;
wire \sld_hub_inst|hub_tdo~607 ;
wire \sld_hub_inst|hub_tdo~610 ;
wire \sld_hub_inst|jtag_state_machine|state~13 ;
wire \sld_hub_inst|hub_tdo ;
wire \sld_hub_inst|hub_tdo~612 ;
wire \altera_internal_jtag~TMSUTAP ;
wire \sld_hub_inst|jtag_state_machine|state[6] ;
wire \sld_hub_inst|jtag_state_machine|state~17 ;
wire \sld_hub_inst|jtag_state_machine|state[7] ;