i2c_altera.vo

从MIC输入一段音频然后

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "12/05/2006 17:29:29"

// 
// Device: Altera EP2C20F484C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	I2C_ALTERA (
	BCLK,
	LRCIN,
	LRCOUT,
	DOUT,
	altera_reserved_tms,
	altera_reserved_tck,
	altera_reserved_tdi,
	SYSCLK,
	RST,
	A_SCLK,
	A_SDIN,
	AMODE,
	DIN,
	ACS,
	altera_reserved_tdo);
input 	BCLK;
input 	LRCIN;
input 	LRCOUT;
input 	DOUT;
input 	altera_reserved_tms;
input 	altera_reserved_tck;
input 	altera_reserved_tdi;
input 	SYSCLK;
input 	RST;
inout 	A_SCLK;
inout 	A_SDIN;
output 	AMODE;
output 	DIN;
output 	ACS;
output 	altera_reserved_tdo;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("I2C_ALTERA_v.sdo");
// synopsys translate_on

wire \inst3|altpll_component|pll~CLK1 ;
wire \inst3|altpll_component|pll~CLK2 ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[4] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_b[1] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[13] ;
wire \inst2|altsyncram_component|auto_generated|altsyncram1|q_a[10] ;
wire \inst8|cnt[15] ;
wire \inst|Select~1080 ;
wire \inst|Select~1083 ;
wire \inst1|divider[6] ;
wire \inst1|clgen|reduce_or~115 ;
wire \inst1|clgen|cnt[5] ;
wire \inst1|clgen|cnt[6] ;
wire \inst1|clgen|cnt[8] ;
wire \inst1|clgen|cnt_one~109 ;
wire \inst1|clgen|cnt[10] ;
wire \inst1|clgen|cnt[12] ;
wire \inst1|clgen|cnt_one~110 ;
wire \inst1|ctrl~272 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[0] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|bypass_reg_out ;
wire \sld_hub_inst|hub_tdo~608 ;
wire \sld_hub_inst|hub_tdo~609 ;
wire \inst1|wb_dat_o[15] ;
wire \inst1|wb_dat_o[14] ;
wire \inst1|wb_dat_o[7] ;
wire \inst|always1~312 ;
wire \inst1|wb_dat_o[6] ;
wire \inst1|wb_dat_o[0] ;
wire \inst1|wb_dat_o[29] ;
wire \inst1|wb_dat_o[25] ;
wire \inst1|wb_dat_o[20] ;
wire \inst1|wb_dat_o[13] ;
wire \inst1|wb_dat_o[17] ;
wire \inst1|wb_dat_o[16] ;
wire \inst1|wb_dat_o[31] ;
wire \inst|always1~319 ;
wire \inst1|wb_dat_o[9] ;
wire \inst8|cnt[14] ;
wire \inst8|cnt[13] ;
wire \inst8|cnt[12] ;
wire \inst8|cnt[11] ;
wire \inst8|cnt[10] ;
wire \inst8|cnt[9] ;
wire \inst8|cnt[8] ;
wire \inst8|cnt[7] ;
wire \inst8|cnt[6] ;
wire \inst8|cnt[5] ;
wire \inst8|cnt[4] ;
wire \inst8|cnt[3] ;
wire \inst8|cnt[2] ;
wire \inst8|cnt[1] ;
wire \inst8|cnt[0] ;
wire \inst8|cnt[0]~129 ;
wire \inst8|cnt[0]~128 ;
wire \inst8|cnt[1]~131 ;
wire \inst8|cnt[1]~130 ;
wire \inst8|cnt[2]~133 ;
wire \inst8|cnt[2]~132 ;
wire \inst8|cnt[3]~135 ;
wire \inst8|cnt[3]~134 ;
wire \inst8|cnt[4]~137 ;
wire \inst8|cnt[4]~136 ;
wire \inst8|cnt[5]~139 ;
wire \inst8|cnt[5]~138 ;
wire \inst8|cnt[6]~141 ;
wire \inst8|cnt[6]~140 ;
wire \inst8|cnt[7]~143 ;
wire \inst8|cnt[7]~142 ;
wire \inst8|cnt[8]~145 ;
wire \inst8|cnt[8]~144 ;
wire \inst8|cnt[9]~147 ;
wire \inst8|cnt[9]~146 ;
wire \inst8|cnt[10]~149 ;
wire \inst8|cnt[10]~148 ;
wire \inst8|cnt[11]~151 ;
wire \inst8|cnt[11]~150 ;
wire \inst8|cnt[12]~153 ;
wire \inst8|cnt[12]~152 ;
wire \inst8|cnt[13]~155 ;
wire \inst8|cnt[13]~154 ;
wire \inst8|cnt[14]~157 ;
wire \inst8|cnt[14]~156 ;
wire \inst8|cnt[15]~158 ;
wire \inst1|clgen|cnt[5]~346 ;
wire \inst1|clgen|cnt[6]~348 ;
wire \inst1|clgen|cnt[8]~352 ;
wire \inst1|clgen|cnt[10]~356 ;
wire \inst1|clgen|cnt[12]~360 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[3] ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[2] ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[0] ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[3] ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[4] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~188 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[1] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~189 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|clear_signal ;
wire \sld_hub_inst|comb~8 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR~142 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR~143 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|no_name_gen~2 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[4] ;
wire \sld_hub_inst|node_ena~18 ;
wire \sld_hub_inst|jtag_ir_register|dffs[0] ;
wire \inst1|shift|data[110] ;
wire \inst1|shift|data[78] ;
wire \inst1|shift|Mux~1424 ;
wire \inst1|shift|Mux~1425 ;
wire \inst1|shift|data[73] ;
wire \inst1|shift|data[121] ;
wire \inst1|shift|data[85] ;
wire \inst1|shift|data[117] ;
wire \inst1|shift|data[81] ;
wire \inst1|shift|data[77] ;
wire \inst1|shift|data[125] ;
wire \inst1|shift|data[84] ;
wire \inst1|shift|data[68] ;
wire \inst1|shift|Mux~1437 ;
wire \inst1|shift|data[88] ;
wire \inst1|shift|Mux~1439 ;
wire \inst1|shift|Mux~1440 ;
wire \inst1|shift|data[80] ;
wire \inst1|shift|data[96] ;
wire \inst1|shift|data[123] ;
wire \inst1|shift|data[103] ;
wire \inst1|shift|data[71] ;
wire \inst1|shift|Mux~1450 ;
wire \inst1|shift|Mux~1451 ;
wire \inst1|shift|Mux~1452 ;
wire \inst1|shift|Mux~1453 ;
wire \inst1|shift|Mux~1454 ;
wire \inst1|shift|data[95] ;
wire \inst1|shift|data[32] ;
wire \inst1|shift|data[17] ;
wire \inst1|shift|data[16] ;
wire \inst1|shift|data[29] ;
wire \inst1|shift|Mux~1476 ;
wire \inst1|shift|Mux~1477 ;
wire \inst1|shift|data[58] ;
wire \inst1|shift|Mux~1490 ;
wire \inst1|shift|Mux~1491 ;
wire \inst1|shift|Mux~1492 ;
wire \inst1|shift|Mux~1493 ;
wire \inst1|shift|data[49] ;
wire \inst1|shift|data[48] ;
wire \inst1|shift|Mux~1494 ;
wire \inst1|shift|Mux~1495 ;
wire \inst1|shift|Mux~1496 ;
wire \inst1|shift|Mux~1497 ;
wire \inst1|shift|data[63] ;
wire \inst1|shift|Mux~1498 ;
wire \inst1|shift|Mux~1499 ;
wire \inst1|shift|s_out~148 ;
wire \inst1|wb_dat[15]~1136 ;
wire \inst1|wb_dat[15]~1137 ;
wire \inst1|wb_dat_o[14]~191 ;
wire \inst1|wb_dat[15]~1138 ;
wire \inst1|wb_dat[14]~1139 ;
wire \inst1|wb_dat[14]~1140 ;
wire \inst1|wb_dat[14]~1141 ;
wire \inst1|ctrl[7] ;
wire \inst1|wb_dat[7]~1142 ;
wire \inst1|ss[7] ;
wire \inst1|wb_dat[7]~1143 ;
wire \inst1|wb_dat[7]~1144 ;
wire \inst1|wb_dat[7]~1145 ;
wire \inst1|wb_dat[4]~1146 ;
wire \inst1|ss[4] ;
wire \inst1|wb_dat[4]~1147 ;
wire \inst1|wb_dat[6]~1150 ;
wire \inst1|ss[6] ;
wire \inst1|wb_dat[6]~1151 ;
wire \inst1|wb_dat[6]~1152 ;
wire \inst1|wb_dat[6]~1153 ;
wire \inst1|wb_dat[5]~1154 ;
wire \inst1|ss[5] ;
wire \inst1|wb_dat[5]~1155 ;
wire \inst1|wb_dat[5]~1156 ;
wire \inst1|wb_dat[2]~1164 ;
wire \inst1|wb_dat[0]~1170 ;
wire \inst1|wb_dat[0]~1171 ;
wire \inst1|wb_dat[0]~1172 ;
wire \inst1|wb_dat[0]~1173 ;
wire \inst1|wb_dat[29]~1176 ;
wire \inst1|wb_dat[29]~1177 ;
wire \inst1|wb_dat[25]~1184 ;
wire \inst1|wb_dat[25]~1185 ;
wire \inst1|wb_dat[24]~1186 ;
wire \inst1|wb_dat[20]~1194 ;
wire \inst1|wb_dat[20]~1195 ;
wire \inst1|wb_dat[18]~1198 ;
wire \inst1|wb_dat_o[13]~125 ;
wire \inst1|wb_dat[13]~1200 ;
wire \inst1|wb_dat[13]~1201 ;
wire \inst1|wb_dat[17]~1202 ;
wire \inst1|wb_dat[17]~1203 ;
wire \inst1|wb_dat[16]~1204 ;
wire \inst1|wb_dat[16]~1205 ;
wire \inst1|wb_dat[31]~1206 ;
wire \inst1|wb_dat[31]~1207 ;
wire \inst1|ctrl[12] ;
wire \inst1|wb_dat_o[9]~129 ;
wire \inst1|wb_dat[9]~1214 ;
wire \inst1|wb_dat[9]~1215 ;
wire \inst1|wb_dat[8]~1216 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[2] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode38w[3] ;
wire \sld_hub_inst|HUB_INFO_REG|add~77 ;
wire \sld_hub_inst|HUB_INFO_REG|add~76 ;
wire \sld_hub_inst|HUB_INFO_REG|add~79 ;
wire \sld_hub_inst|HUB_INFO_REG|add~78 ;
wire \sld_hub_inst|HUB_INFO_REG|add~81 ;
wire \sld_hub_inst|HUB_INFO_REG|add~80 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[0]~8 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~190 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter~163 ;
wire \sld_hub_inst|HUB_INFO_REG|add~83 ;
wire \sld_hub_inst|HUB_INFO_REG|add~82 ;
wire \sld_hub_inst|HUB_INFO_REG|add~84 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter~164 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~191 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[1] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2] ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR~144 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR~145 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1]~203 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter~204 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0]~6 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter~205 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|reduce_nor~19 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0]~206 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~103 ;
wire \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[4]~104 ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[2] ;
wire \inst1|shift|add~1970 ;
wire \inst1|shift|add~1980 ;